Patent
Electrically erasable programmable non-volatile semiconductor memory device having select gates and small number of contact holes
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TLDR
In this paper, a lamination type memory cell and a select transistor having a floating gate were used to construct a first polysilicon film of a high resistance, which is not necessary to form a contact hole in the gate wire of the select transistor between a cell array.Abstract:
The structure of the invention employs a lamination type memory cell and a lamination type select transistor having a floating gate. Since no contact holes are formed in a first polysilicon film of a high resistance, it is not necessary to form a contact hole in the gate wire of the select transistor between a cell array. A floating gate is beforehand charged with electricity so that the select transistor cab have a positive threshold value. Alternatively, an impurity is introduced into the channel region of the select transistor so that the neutral threshold voltage of the transistor after radiation of ultraviolet rays can have a positive value.read more
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Patent
Electrically erasable programmable read-only memory with NAND cell structure
Tetsuo Endoh,Riichiro Shirota,Masaki Momodomi,Tomoharu Tanaka,Fujio Masuoka,Shigeyoshi Watanabe +5 more
TL;DR: In this article, an erasable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate, each of which has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain.
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TL;DR: In this paper, an electrically erasable programmable semiconductor memory array for high density including a plurality of column lines and reference lines perpendicular to the column lines, was presented, where the drain-source paths of the first or second transistor and the floating gate transistors in each memory string were connected in series.