Patent
Enhancement mode, Schottky-barrier gate gallium arsenide field effect transistor
TLDR
In this article, a gate metalization is applied to the FET channel region, and the gate is exposed to the bombardment of protons with sufficiently high energy to penetrate through the gate and enter the channel region.Abstract:
Disclosed is a new process for fabricating field effect transistors, and particularly enhancement mode and depletion mode Schottky-gate field effect transistors. The process includes the steps of forming a thin layer of gate metalization over the FET channel region, and this gate metalization is then exposed to the bombardment of protons with sufficiently high energy to penetrate through the gate metalization layer and enter the channel region of the FET and there produce deep level energy traps in the channel region. These traps serve to tie up carriers and create donor and acceptor vacancy complexes in the FET channel. This step has the effect of raising the resistivity of the FET channel and is used to make the FET device non-conducting with zero voltage on the gate metalization, i.e., an enhancement mode device.read more
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Plasma Processing Apparatus
TL;DR: In this paper, a plasmas processing apparatus consisting of plural layers formed in stack one upon another on a semiconductor wafer placed on the sample holder located in the process chamber is etched with plasma generated by supplying high frequency power to the electrode disposed in a sample holder, and a power source for supplying power at different values to the ring-shaped electrode depending on the sorts of layers of the layer structure.
Patent
Vertical type MOS transistor and method of formation thereof
TL;DR: In this article, a vertical MOS transistor has been shown to have its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed.
Patent
Selective epitaxial etch planar processing for gallium arsenide semiconductors
TL;DR: In this paper, a method of fabricating gallium arsenide circuits or devices in which source and drain contact areas are deposited using vapor phase epitaxy techniques through holes in a refractory mask.
Patent
Selective lift-off technique for fabricating gaas fets
TL;DR: In this article, the MBE growth of epitaxial layers on selected areas of a growth surface is achieved by masking portions of the surface with an amorphous material and directing molecular beams at the masked surface so that a polycrystalline layer deposits on the mask and an epi-layer grows in the unmasked zones.
Patent
Schottky-gate field-effect transistor and fabrication process therefor
TL;DR: In this article, a Schottky-gate field effect transistor and related fabrication process is described, where thin ion implanted surface stabilization regions are formed between source and gate electrodes and gate and drain electrodes of the device and to a thickness of between 100 and 1,000 angstroms.
References
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Patent
Methods of manufacturing a semiconductor device
J Shannon,J Kerr +1 more
TL;DR: In this article, a method of making a semiconductor device which combines ion implantation with another process of forming an impurity-containing semiconductor region is described, which yields improved semiconductor devices.
Patent
Fabrication of insulated gate field-effect transistors involving ion implantation
TL;DR: In this article, an insulated gate field effect transistor is made which utilizes both Schottky barrier connections and ion-implanted zones, and the resultant structure incorporates source and drain zones, which are formed by ion implantation and whose spacing is fixed by the gate electrode.
Patent
Proton enhanced diffusion methods
TL;DR: In this article, the authors present an example of the use of PROTON ENHANCED DIFFUSION in the construction of a carriere for a PEDESTAL TRANSISTOR.
Patent
Methods of manufacturing semiconductor devices
TL;DR: In this paper, a tetrode insulated gate field effect transistor is described, where a thin conductive layer is applied on the surface parts or surface adjacent parts at which the ion beam is to be directed.
Patent
Method for making n-type layers in gallium arsenide at room temperatures
TL;DR: In this paper, a method for making an N-type LAYER in a GALLIUM ARSENIDE SUBSTRATE is described, and a set of SULPHUR IONS are placed into the GALLUMENIDE substrategies at room temperature.