Patent
Extended bus controller
Masayuki Nakamura,Fujiya Ikuta +1 more
TLDR
In this article, an extended bus controller includes a base module including at least a first peripheral control unit connected to a base bus, a central processing and controlling unit, and a memory unit.Abstract:
An extended bus controller includes a base module including at least a first peripheral control unit connected to a base bus, a central processing and controlling unit, and a memory unit; an extension module including at least a second peripheral control unit connected to an extended bus; a connection bus interconnecting the base bus of the base module and the extended bus of the extension module; a direct memory access control unit provided for at least one of the base module and the extension module for directly controlling data transfer between the first and second peripheral control units and the memory unit; a first master clock generator unit for supplying first master clocks to the direct memory access control unit and controlling the direct memory access control unit, the first master clocks having a first frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the first peripheral control unit and the memory unit; and a second master clock generator unit for supplying second master clocks to the direct memory access control unit and controlling the direct memory access control unit, the second master clocks having a second frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the second peripheral control unit and the memory unit.read more
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Patent
Single-chip microcomputer
Shumpei Kawasaki,Yasushi Akao,Kouki Noguchi,Atsushi Hasegawa,Hiroshi Ohsuga,Keiichi Kurakazu,Kiyoshi Matsubara,Akio Hayakawa,Yoshitaka Ito +8 more
TL;DR: In an evaluation single-chip microcomputer which includes circuit elements connected to an internal bus and capable of storing data or of arithmetic operation, the contents of the circuit elements being required to be known outside of the microcomputer, a control circuit decodes instructions supplied through theInternal bus and produces control signals for controlling the operations of the Circuit elements.
Patent
SCSI interface employing bus extender and auxiliary bus
TL;DR: A bus interface employs a bus extender for connecting an auxiliary bus to a single port on a main bus in such a way that the extender sends message data signals received over the one bus directly onto the other bus without modification.
Patent
Microcomputer having multiple bus structure coupling CPU to other processing elements
Shumpei Kawasaki,Yasushi Akao,Kouki Noguchi,Atsushi Hasegawa,Hiroshi Ohsuga,Keiichi Kurakazu,Kiyoshi Matsubara,Akio Hayakawa,Yoshitaka Ito +8 more
TL;DR: In this article, a single-chip microcomputer consisting of a first bus having a central processing unit and a cache memory connected therewith, a second bus having an access control circuit and an external bus interface connected there with, a break controller for connecting the first bus and the second bus selectively, and a third bus with a peripheral module connected there and having a lower-speed bus cycle than the bus cycles of the first and second buses.
Patent
High performance multifunction direct memory access (DMA) controller
TL;DR: In this article, a direct memory access (DMA) controller with memory-to-memory data transfer capability, a programmable fixed priority scheme, programmable wait state, a buffer chaining mode, a cascade-master mode, separate channels for internal and external devices, and programmable 8 or 16 bit requester bus size.
Patent
High-performance DMA controller
TL;DR: In this article, a high-performance DMA controller for controlling data transfer between a main storage means holding various kinds of data and a plurality of local storage means, comprises an interface for generating a control signal for the main storage mean, a data I/O unit for controlling the data, a parameter holding unit for holding the parameters required for execution of data transfer, and a start command receiver for receiving a start/stop command of the data transfer controller.
References
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Patent
Peripheral unit controller.
TL;DR: In this article, the authors propose a synchronization scheme that allows each microprocessor (300, 307) to run its own diagnostics independently, and to synchronize itself with the other microprocessor of the pair.
Patent
Multiprocessor computer system
TL;DR: In this paper, the memory bus means are configurated to allow direct data transfer between any memory fraction of central processing unit systems without interfering with the central processing units that being controlled by direct memory access control means.
Patent
Information processing system
TL;DR: In this paper, an information processing system consisting of a main memory unit, an arithmetic control unit, and a plurality of input/output units, is described, where the data transfer between two units connecting to the first and second buses in time sharing and multiplexing mode.
Patent
Multi-microcomputer system with direct store access
TL;DR: In this article, the authors describe a multi-microcomputer system employing a direct memory access controller (DMA) for access to the direct memory of the individual microcomputers, where the data buses and address buses are interconnected by means of bus separator stages.
Patent
Extension of data bus
TL;DR: In this paper, a data bus extension device with a simple logic circuit without ineffective access time by lowering the frequency of a synchronizing clock signal temporally only in the access time is presented.