Journal ArticleDOI
Fault detection in combinational networks by Reed-Muller transforms
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TLDR
An upper bound is found for the minimum number of test patterns required to detect a fault in combinational networks based on Reed-Muller (RM) transforms.Abstract:
A new approach for fault detection in combinational networks based on Reed-Muller (RM) transforms is presented. An upper bound on the number of RM spectral coefficients required to be verified for detection of multiple stuck-at-faults and single bridging faults at the input lines of an n-input network is shown to be n. The time complexity (time required to test a network) for detection of multiple terminal faults and the storage required for storing the test are determined. An upper bound is found for the minimum number of test patterns required to detect a fault. The authors present standard tests based on this result, with a simple test generation procedure and upper bounds on minimal numbers of test patterns. >read more
Citations
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Journal ArticleDOI
Effective computer methods for the calculation of Rademacher-Walsh spectrum for completely and incompletely specified Boolean functions
TL;DR: The algorithm and its implementation provide the fastest and most comprehensive program (having many options) known to the authors for the calculation of the Rademacher-Walsh transform.
Journal ArticleDOI
Easily testable realizations for generalized Reed-Muller expressions
TL;DR: In this article, the authors presented a testable AND-EXOR network using generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-muller expression (PPRMs).
Journal ArticleDOI
A minimal universal test set for self-test of EXOR-Sum-of-Products circuits
TL;DR: A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/ outputs of the realization are given.
Proceedings ArticleDOI
Easily testable realizations for generalized Reed-Muller expressions
TL;DR: In this article, the authors presented a testable AND-EXOR network with generalized Reed-Muller expressions (GRMs) instead of PPRMs, which can detect multiple stuck-at-faults under the assumption that the faults occur in at most one part, either the literal part, an AND part, the EXOR part, or the check part.
Patent
Methods and computer programs for minimizing logic circuit design using identity cells
T. Raju Damarla,Wei Su +1 more
TL;DR: In this article, the I-cell term representation is used to simplify logic circuit design by combining and minimizing Identity cells and thereby reducing the number of gates in the logic circuit, which can be used to represent sub-functions such as ABC+ABC.
References
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Introduction to coding theory
TL;DR: This third edition has been revised and expanded, including new chapters on algebraic geometry, new classes of codes, and the essentials of the most recent developments on binary codes.
Journal ArticleDOI
Easily Testable Realizations ror Logic Functions
TL;DR: A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties of "easily testable networks".
Journal ArticleDOI
Testing by Verifying Walsh Coefficients
TL;DR: Testing of logic networks by verifying the Walsh coefricients of the outputs is explored, and measurement of one of these can detect arbitrarily many input leads stuck, and just two measurements can detect any single stuck-at fault in appropriately designed networks.