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Fermi-threshold field effect transistors including source/drain pocket implants and methods of fabricating same

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TLDR
In this article, a Fermi-FET includes a drain extension region of the same conductivity type as the drain region and a drain pocket implant region of opposite conductivities type from drain region.
Abstract
A Fermi-FET, including but not limited to a tub-FET, a contoured-tub Fermi-FET or a short channel Fermi-FET includes a drain extension region of the same conductivity type as the drain region and a drain pocket implant region of opposite conductivity type from the drain region The drain pocket implant region acts as a drain field stop to reduce or prevent drain-to-source field reach-through Reduced low drain field threshold voltage, significantly reduced drain induced barrier lowering and reduced threshold dependence on channel length may be obtained, resulting in higher performance in short channels

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References
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Patent

Method of making semiconductor devices

TL;DR: In this article, a method for making an IGFET is described, which utilizes impurity ion implantation into the surface channel to determine the conductivity of the IC's surface channel.
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Fermi threshold field effect transistor

TL;DR: In this paper, the authors proposed a Fermi threshold FET with a threshold voltage that is independent of oxide thickness, channel length, drain voltage, and substrate doping, which can be manufactured using relaxed ground-rules to provide low cost, high yield devices.
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Fermi threshold silicon-on-insulator field effect transistor

TL;DR: In this paper, a Fermi threshold SOI FET with a threshold voltage that is independent of oxide thickness, channel length, drain voltage, and substrate channel doping is presented.
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Double implanted LDD transistor self-aligned with gate

TL;DR: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer is presented in this paper.
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MOSFET with reduced short channel effect

TL;DR: In this paper, a gate-insulating MOSFET provided with a gate insulating film formed on a semiconductor surface between a source region and a drain region, a gate electrode formed on the gate and a channel region sandwiched between the source and the drain regions and made up of a first layer and a second layer is disclosed.