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Ferroelectric memory device

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TLDR
In this article, a ferroelectric memory device utilizing the remanent polarization of a thin, active ferro-electric film was proposed to control the surface conductivity of a bulk semiconductor and perform the memory function.
Abstract
A ferroelectric memory device utilizing the remanent polarization of a thin, ferroelectric film to control the surface conductivity of a bulk semiconductor and perform the memory function. The structure of the device is similar to a conventional MIS field effect transistor with the exception that the gate insulating layer is replaced by a thin film of active ferroelectric material comprising a reversably polarizable dielectric exhibiting hysteresis.

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Citations
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Patent

Self restoring ferroelectric memory

TL;DR: In this article, a semiconductor memory with a ferroelec-tric capacitor having one plate coupled to a bit line by a FET and another plate coupled on a plate line is described.
Journal ArticleDOI

Room-temperature ferroelectric resistive switching in ultrathin Pb(Zr 0.2 Ti 0.8)O3 films.

TL;DR: The present approach uses metal-ferroelectric-metal devices at room temperature and, therefore, significantly advances the use of ferro electric-based resistive switching.
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Ferroelectric capacitor and memory cell including barrier and isolation layers

TL;DR: In this paper, a ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate, which includes a diffusion barrier layer above the surface of the substrate for preventing the materials of the capcacitor from contaminating the substrate or MOS device.
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Ferroelectric thin film material, method of deposition, and devices using same

TL;DR: In this article, a polarizing thin film of BaMF4 on a substrate is described, and a nonvolatile NDRO and DRO memory cell and methods for depositing the thin film are described.
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A ferroelectric dynamic random access memory

TL;DR: In this paper, a memory including an array of memory cells (20), each of which includes a ferroelectric field effect transistor (FET) as its memory element, and sense and refresh circuitry (32) connected to the array memory cells to read stored data within each cell by sensing source-to-drain conductivity of the FET and to refresh the stored data.
References
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Patent

Electronic memory circuit employing semiconductor memory elements and a method for writing to the memory element

TL;DR: In this article, a memory matrix in which a plurality of MIS transistors are arranged in a matrix array and have their gate and source-drain electrodes connected to row-and-column drive lines is described.