Patent
Gate-coupled MOSFET ESD protection circuit
Shi-Tron Lin,Wei-Fan Chen +1 more
TLDR
In this paper, a gate-coupled MOSFET ESD protection circuit was proposed, where a pulldown element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event.Abstract:
A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.read more
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Patent
Semiconductor Integrated circuit
Yutaka Shinagawa,Takeshi Kataoka,Eiichi Ishikawa,Toshihiro Tanaka,Kazumasa Yanagisawa,Kazufumi Suzukawa +5 more
TL;DR: In this article, a semiconductor integrated circuit (SIC) has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the SIC.
Patent
Electrostatic discharge protection element
Harald Gossner,Christian Russ +1 more
TL;DR: A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions.
Patent
ESD protection circuit for radio frequency input/output terminals in an integrated circuit
TL;DR: In this article, an integrated circuit comprises an ESD protection circuit including an inductor coupled between an input terminal and a ground terminal at which an RF signal is applied, and the inductor is designed so as to provide a sufficient current capability required in typical ESD events.
Patent
Electrostatic discharge device with variable on time
TL;DR: In this article, an electrostatic discharge device, typically referred to as a power clamping circuit, is used for minimizing the effects of an initial ESD event as well as providing protection against subsequent ESD events.
Patent
High voltage ESD power clamp
TL;DR: In this article, the authors proposed a method for protecting against electrostatic discharge by configuring a gate of at least one upper transistor of a transistor network connected between power rails to be biased to a prescribed value.
References
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Patent
Schmitt trigger-configured ESD protection circuit
William R. Young,Gregg D. Croft +1 more
TL;DR: A Schmitt trigger-configured overvoltage protection circuit has a hysteresis turn-on, turn-off characteristic that minimizes its sensitivity to noise, and is effective to protect an integrated circuit against a DC over-voltage condition, and electrostatic discharge-based transients, while allowing hot insertion of a device containing the clamping circuit into an already powered-up system.
Patent
Voltage level triggered ESD protection circuit
TL;DR: In this article, a voltage level triggered ESD protection circuit is proposed, which does not consume any DC current either in the powered up or powered down states, and is interfaceable to a live bus when the system it is connected to is powered down.