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Generalized history table for branch prediction (in pipeline computers)

J.J. Losq
- Vol. 1
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TLDR
The idea set forth is for all the information that allows for a highly accurate prediction of branches to be kept in a generalized table.
Abstract
The idea set forth is for all the information that allows for a highly accurate prediction of branches to be kept in a generalized table.

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Citations
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Proceedings ArticleDOI

Trace cache: a low latency approach to high bandwidth instruction fetching

TL;DR: It is shown that the trace cache's efficient, low latency approach enables it to outperform more complex mechanisms that work solely out of the instruction cache.
Book

Machine organization of the IBM RISC System/6000 processor

TL;DR: The IBM RISC System/6000 processor as discussed by the authors is a second-generation RISC processor which reduces the execution pipeline penalties caused by branch instructions and also provides high floating-point performance.
Proceedings ArticleDOI

Applying decay strategies to branch predictors for leakage energy savings

TL;DR: The strategies for exploiting spatial and temporal locality to make decay effective for bimodal, gshare, and hybrid predictors, as well as the branch target buffer demonstrate that decay techniques apply more broadly than just to caches, but that careful policy and implementation make the difference between success and failure in building decay-based branch predictors.
Journal ArticleDOI

Implementing branch-predictor decay using quasi-static memory cells

TL;DR: This paper demonstrates that decay techniques can apply to more than just caches, with the branch predictor and BTB as an example, and shows decay can either be implemented at the architectural level, or with a wholesale replacement of static storage cells with quasi-static storage cells, which naturally implement decay.