Journal ArticleDOI
I DDQ testing as a component of a test suite: the need for several fault coverage metrics
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TLDR
The argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults, to demonstrate the need for increasingly stringent fault coverage requirements.Abstract:
This article is concerned with the role of I DDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults. To demonstrate the need for increasingly stringent fault coverage requirements, an analysis is given of the relationship between quality, fault coverage and chip area. This analysis shows that as chip area increases, fault coverage must also increase to maintain constant quality levels. Data are then presented from a production part tested with Iddq scan, timing and functional tests. To realistically fault grade I DDQ tests, three different coverage metrics are considered. The data show differences in tester failures compared to these coverage metrics, depending on whether one uses total Iddq failures (parts which fail Iddq regardless of whether they fail other tests as well) or unique IDdq failures (parts which fail only Iddq). The relative effectiveness of the different components of the full test suite are analyzed and it is demonstrated that no component can be removed without suffering a reduction in quality.read more
Citations
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Proceedings Article
Extraction and Simulation of Realistic CMOS Faults using
TL;DR: FXT as mentioned in this paper is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Proceedings ArticleDOI
Defect classes-an overdue paradigm for CMOS IC testing
TL;DR: In this paper, the authors propose a comprehensive test paradigm for testing CMOS ICs that uses defect classes based on measured defect electrical properties, and describe test pattern requirements for each defect class and propose a test paradigm.
Journal ArticleDOI
I DDQ testing: A review
TL;DR: The use of IDDQ testing for IC quality improvement through increased defect and fault detection is described, and implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis.
Book ChapterDOI
Iddq testing : A review
TL;DR: Quiescent power supply current (IDDQ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis.
Proceedings ArticleDOI
REDO-random excitation and deterministic observation-first commercial experiment
Michael R. Grimaila,Sooryong Lee,Jennifer Dworak,Kenneth M. Butler,B. Stewart,Hari Balachandran,B. Houchins,V. Mathur,Jaehong Park,Li-C. Wang,M.R. Mercer +10 more
TL;DR: For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75 K logic gates.
References
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Journal ArticleDOI
Cost-size optima of monolithic integrated circuits
TL;DR: In this article, a generalized cost-size relationship is derived for a monolithic circuit consisting of N identical components, taking into account variations in component density, yield, and assembly costs with N. The results indicate that when systems requirements make it desirable to include larger numbers of components in one package than the optimum for one monolith, wired-chip schemes are preferable to single monoliths, the optimum chip size being smaller than that for a simple monolith.
Journal ArticleDOI
The use and evaluation of yield models in integrated circuit manufacturing
TL;DR: In this article, the development and refinement of net-die-per-wafer yield models during the past 25 years are reviewed, and the models are tested for accuracy by comparison with actual yield data from seven separate chip companies.
Proceedings ArticleDOI
Extraction and simulation of realistic CMOS faults using inductive fault analysis
F.J. Ferguson,John Paul Shen +1 more
TL;DR: FXT is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Proceedings Article
Extraction and Simulation of Realistic CMOS Faults using
TL;DR: FXT as mentioned in this paper is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.