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Proceedings ArticleDOI

Implementation of low-power multifunctional circuit for varying operand lengths

TLDR
A 64-bit controllable decision block is presented, which can operate on different operands and is good for multimedia applications because many algorithms function on operands of changing data sizes.
Abstract
In this paper, we present a low-power multifunctional circuit for varying operand lengths. In this multifunctional circuit have two blocks 1) Input Selection Block 2) Decision Block. By using these two blocks, we can reduce the delay and the dynamic power due to decrease power supply voltage and frequency. The multifunctional circuit can perform four different operations like priority encoder, increment, 2's complement and decrement. A 64-bit controllable decision block is presented, which can operate on different operands. Our technique is good for multimedia applications because many algorithms function on operands of changing data sizes.

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References
More filters
Proceedings ArticleDOI

A family of adders

S. Knowles
TL;DR: These are end cases of a large family of addition structures, all of which share the attractive property of minimum logical depth, and can thus usually achieve a more attractive combination of speed and area/power cost than either of the known end-cases.
Proceedings ArticleDOI

A taxonomy of parallel prefix networks

TL;DR: A three-dimensional taxonomy is presented that not only describes the tradeoffs in existing parallel prefix networks but also points to a family of new networks that are competitive in latency and area for some technologies.
Book

Fundamentals of Digital Logic with Verilog Design

TL;DR: Fundamentals of Digital Logic With Verilog Design teaches the basic design techniques for logic circuits and emphasizes the synthesis of circuits and explains how circuits are implemented in real chips.
Journal ArticleDOI

Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques

TL;DR: Results indicate that the proposed 256-bit priority encoder and the proposed 64-bit incrementer/decrementer can operate up to 116 and 139 MHz when they are designed based on a 0.6-/spl mu/m CMOS technology.
Proceedings ArticleDOI

A new parallel technique for design of decrement/increment and two's complement circuits

TL;DR: The technique is shown to be highly efficient of both in terms silicon area consumption and time, and more interestingly, it is shown that the operation delay is almost independent of the word size, and hence the method is best used for high-density codes.