Montgomery reduction is a well-known optimization technique for modular reduction over prime fields. However, it has rarely been used for national institute of standards and technology (NIST) prime fields, because the special structure of NIST primes enables fast reduction that requires fewer computations than Montgomery reduction. In this study, we rediscover the Montgomery reduction for NIST primes and propose a new modular reduction method by applying partial modular reduction to Montgomery reduction. Using this new modular reduction method and other optimization techniques, such as pipelining and parallel processing, we propose an efficient elliptic curve cryptography (ECC) coprocessor over NIST prime fields. The implementation results indicate that the proposed coprocessor can perform one elliptic curve point multiplication in 0.055 ms with only 194.7 k gate counts. This is a considerably higher speed per area compared to previous research.

Improving ring-oscillator-based true random number generators using multiple sampling

ECC Coprocessor Over a NIST Prime Field Using Fast Partial Montgomery Reduction

This brief proposes a compact and fast elliptic curve cryptography coprocessor using affine coordinates. Although using affine coordinates requires compute-intensive modular inversion (ModInv), the proposed coprocessor can be accelerated using the improved ModInv. In addition, the study proposes a novel point multiplication method that is effective in preventing simple power analysis when affine coordinates are used. Using point randomization, the proposed coprocessor is also resistant to statistical power analysis (PA) such as differential PA (DPA) and correlation PA (CPA), and it requires 60 k gate counts and can perform one elliptic curve point multiplication within 1 ms at the maximum clock frequency.

Lightweight ECC Coprocessor With Resistance Against Power Analysis Attacks Over NIST Prime Fields

We propose a novel computer architectural concept of instruction overloading to support block ciphers. Instead of adding new instructions, we extend only the execution of some existing instructions. The proposed method allows a central processing unit core to execute different operations for the same instructions, depending on the address of the data, similar to operator overloading in object-oriented languages. We first present an extension for the AES algorithm, then we demonstrate its enhanced applicability with two further extensions supporting multiple block ciphers and hardware masking. The first extension for AES is also applicable to add/AND-rotate-XOR-based block ciphers such as SIMON. The AES and SIMON encryption speed, on this extended core, is at least doubled and is significantly less affected by memory latency. In addition, the AES encryption code requires only 18% of the memory of the previous software implementation. The second extension can further support various block ciphers defined over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ), and the SM4 encryption speed is increased by at least 182%. The third extension provides correlation power analysis (CPA) resistance with a 66.6% area overhead but almost no speed overhead, whereas a typical software anti-CPA AES implementation requires at least hundreds of times the execution time. 

Improving ring-oscillator-based true random number generators using multiple sampling

Citations

ECC Coprocessor Over a NIST Prime Field Using Fast Partial Montgomery Reduction

Lightweight ECC Coprocessor With Resistance Against Power Analysis Attacks Over NIST Prime Fields

Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading

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