Input/output system for multiprocessors

TLDR: In this paper, the authors present a digital computer system which employs a plurality of host processors (33), at least two system buses (35), and a plurality (41) of peripheral input/output ports.

Abstract: In a digital computer system which employs a plurality of host processors (33), at least two system buses (35) and a plurality of peripheral input/output ports, an input/out­put system is provided whereby ownership of the input/output channels (109) is shared. The device controller (41) employs a first port controller (43-0) having a first ownership latch, a second port controller (43-1) having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controlIer which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI) (111), and at least provi­sion for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.