Proceedings ArticleDOI
Instruction fetch energy reduction using loop caches for embedded applications with small tight loops
Lea Hwang Lee,Bill Moyer,John H. Arends +2 more
- pp 267-269
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TLDR
This paper proposes using a small instruction buffer, also called a loop cache, to save power in caches, which has no address tag store and knows precisely whether the next instruction request will hit in the loop cache well ahead of time.Abstract:
A fair amount of work has been done in recent years on reducing power consumption in caches by using a small instruction buffer placed between the execution pipe and a larger main cache. These techniques, however, often degrade the overall system performance. In this paper, we propose using a small instruction buffer, also called a loop cache, to save power. A loop cache has no address tag store. It consists of a direct-mapped data array and a loop cache controller. The loop cache controller knows precisely whether the next instruction request will hit in the loop cache, well ahead of time. As a result, there is no performance degradation.read more
Citations
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Proceedings ArticleDOI
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
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Book
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Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache
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References
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Proceedings ArticleDOI
The filter cache: an energy efficient memory structure
TL;DR: Experimental results across a wide range of embedded applications show that the filter cache results in improved memory system energy efficiency, and this work proposes to trade performance for power consumption by filtering cache references through an unusually small L1 cache.
Proceedings ArticleDOI
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TL;DR: In this article, the authors used an energy-delay metric to compare many of the proposed techniques and provided insight into some of the basic trade-offs in low-power design, including trade speed for power, do not waste power, and find a lower power problem.
Proceedings ArticleDOI
Cache design trade-offs for power and performance optimization: a case study
Ching-Long Su,Alvin M. Despain +1 more
TL;DR: This paper examines performance and power trade-offs in cache designs and the effectiveness of energy reduction for several novel cache design techniques targeted for low power.
Patent
Data processing system having a cache and method therefor
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Proceedings ArticleDOI
Low-cost branch folding for embedded applications with small tight loops
TL;DR: This paper proposes a hardware technique for folding branches when executing small loops, based on the detection and utilization of certain short backward branch instructions (sbb).