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Integrated circuit insulator and method
Kelly J. Taylor,Mona M. Eissa +1 more
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In this paper, a intermetal level dielectrics with fluorinated polymers of parylene (142) between metal lines (112-120), and vapor deposition method for the polymerization followed by fluorination of the polymers.Abstract:
A intermetal level dielectrics with fluorinated (co)polymers of parylene (142) between metal lines (112-120), and vapor deposition method for the (co)polymerization followed by fluorination of the (co)polymers.read more
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Orienting, positioning, and forming nanoscale structures
TL;DR: In this paper, a first copolymer is provided and a substrate is provided having an energetically neutral surface layer with at least one trough integrally disposed thereon with sidewalls.
Patent
Film-forming composition and insulating film-forming material
Masahiko Ebisawa,Satoko Hakamazuka,Michinori Nishikawa,Mayumi Tsunoda,Kinji Yamada,欣司 山田,政彦 海老沢,聡子 袴塚,通則 西川,真由美 角田 +9 more
TL;DR: In this paper, the problem of obtaining a film-forming composition which excels in the mechanical properties of a coated film and can effect firing of the coated film in a short period of time and exhibits a very low dielectric constant as the interlaminar insulating film material in semiconductor elements and the like.
Patent
Methods for chemical mechanical polish of organic polymer dielectric films
Neil Hendricks,Daniel L. Towery +1 more
TL;DR: In this article, a process for the formation and planarization of polymeric dielectric films on semiconductor substrates and for achieving high chemical mechanical polish removal rates when planarizing these films is presented.
Patent
Method of positioning patterns from block copolymer self-assembly
TL;DR: In this paper, a method for controlling alignment and registration of lamellae formed from self-assembly of block copolymers is proposed, the method comprising the steps of obtaining a substrate having an energetically neutral surface layer comprising a first topographic phase pinning pattern and a second topographic guiding pattern.
Patent
Process to improve adhesion of HSQ to underlying materials
Chung-Long Chang,Syun-Ming Jang +1 more
TL;DR: In this paper, a process for forming an intermetal dielectric, (IMD), layer, comprised of an overlying silicon oxide layer, and an underlying low k dielectrics layer such as hydrogen silsesquioxane, (HSQ), has been developed.
References
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Patent
Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
TL;DR: In this article, a planar intermetal dielectric layer (IMD) for multilevel electrical interconnections on ULSI circuits is achieved by forming metal lines on which is deposited a conformal PECVD oxide.
Patent
Vapor deposition of parylene-F using 1,4-bis (trifluoromethyl) benzene
TL;DR: A PA-F polymer film is formed using a mixture of 1,4-bis (trifluoromethyl) benzene (TFB) and a halogen initiator.
Patent
Method of forming a multilevel dielectric
TL;DR: In this article, a planar dielectric layer over an interconnect pattern is constructed, which requires fewer processing steps and has a lower dielectoric constant than is obtained in the prior art.
Patent
Processes for the preparation of octafluoro-[2,2] paracyclophane
William R. Dolbier,X. X. Rong +1 more
TL;DR: In this paper, a process for the preparation of octafluoro-[2,2]paracyclophane includes contacting a reactant selected from the group consisting of 1,4-bis (bromodifluoromethyl)benzene (dibromide), 1, 4-bis(chlorodiflormide, dichloride), and 1, 2-bromide with trimethylsilyltributyltin (TMSTBT) (a reducing agent) and fluoride ions in a refluxing solution of
Patent
Fluorine doped silicon oxide process
TL;DR: In this paper, a process for forming a fluorine-containing silicon oxide film on a substrate by plasma-enhanced chemical vapor deposition using a fluorinated silicon source of the formula is described.