Patent
Integrated circuit structure and method for making integrated circuit structure
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TLDR
In this article, a method for simultaneously completing the formation of a contact, an interconnect, a gate and a source or drain is disclosed, where a diffused silicon area is connected directly to a polysilicon member by conductive silicon.Abstract:
In connection with the fabrication of an integrated circuit, a method for simultaneously completing the formation of a contact, an interconnect, a gate and a source or drain is disclosed. An integrated circuit field effect structure wherein a diffused silicon area is connected directly to a polysilicon member by conductive silicon and more specifically the source or drain of one device is directly and continuously connected to the gate of an adjacent device by a conductive silicon member.read more
Citations
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Patent
Low voltage one transistor flash EEPROM cell using Fowler-Nordheim programming and erase
TL;DR: In this article, a programmable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of operating using low voltages is presented.
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Programmable semiconductor integrated circuitry including a programming semiconductor element
Toshiaki Masuhara,Osamu Minato,Katsuhiro Shimohigashi,Hiroo Masuda,Hideo Sunami,Yoshio Sakai,Yoshiaki Kamigaki,Eiji Takeda,Yoshimune Hagiwara +8 more
TL;DR: In this paper, a programmable semiconductor integrated circuitry including a circuit programming element is disclosed, which can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.
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Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines
TL;DR: In this paper, a process for producing VLSI (very large scale integrated) circuits employs techniques of selfaligned gates and contacts for FET devices and self-aligned contacts for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate.
Journal ArticleDOI
One-device cells for dynamic random-access memories: A tutorial
TL;DR: In this paper, the evolutionary development of one-device cells for dynamic random access memory (RAM) integrated circuits is described in a systematic manner, including structural features such as contact via formation, bit-line and word-line pitch, metal step coverage and cell placement along the bit line.
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MIS semiconductor device and method of manufacturing the same
TL;DR: In this article, a metal-insulator semiconductor (MIS) device is manufactured by initially forming, on a semiconductor substrate, an insulating film having a hole therethrough and depositing silicon on the substrate to form a first monocrystalline silicon film in the hole and a poly-crystalline poly-poly-silicon film on the insulating material.
References
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Patent
Igfet comprising n-type silicon substrate, silicon oxide gate insulator and p-type polycrystalline silicon gate electrode
Boyd G Watkins,Michael J Selser +1 more
TL;DR: In this article, a polycrystalline semiconductor surface layer is employed as a mask for the diffusion of the source and drain regions, thereby insuring automatic alignment between the gate electrode and the source or drain regions.
Patent
Method for fabricating field-effect transistor devices and integrated circuit modules containing the same by selective diffusion of activator impurities through preselected portions of passivating-insulating films
Dale M. Brown,William E Engeler +1 more
TL;DR: In this article, a large region of OPPOSITE-CONDUCTIVITY-type SEMICONDUCTOR is formed by DIFFUSION THROUGH BOTH CONDUCTING and OXIDE FILMS.