Eiji Takeda

TL;DR: In this article, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFETs: a graded drain junction structure and an offset gate structure.

TL;DR: In this article, a vertical semiconductor memory cell with a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration has been presented for use in a ultra-high density integration DRAM of a Gbit class.

TL;DR: In this paper, a programmable semiconductor integrated circuitry including a circuit programming element is disclosed, which can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.

TL;DR: In this paper, a semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics, and necessary electrodes such as the gate electrode and necessary insulating layers can be added at the thin semiconductor layer, and can maintain the necessary amount of electric current by securing the height of the semiconductor layers.

TL;DR: In this paper, a semiconductor memory device whose data hold condition is not affected due to degradation of transistor characteristics by minimizing leakage charges and the switching transistor size is presented, where the memory cell charge holding electrode is insulated from the remaining memory cell structure, particularly the source drain leakage path.