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Patent

Latching circuit, and flip-flop circuit using this latching circuit

Sakagami Kenji
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TLDR
In this paper, the authors propose to execute a high speed operation by connecting each input terminal and output terminal of two clock gates, respectively, and providing a data transfer gate on each connecting point of the input terminals and the output terminals, respectively.
Abstract: 
PURPOSE:To execute a high speed operation by connecting each input terminal and output terminal of two clock gates, respectively, and providing a data transfer gate on each connecting point of the input terminal and the output terminal, respectively. CONSTITUTION:When a clock signal phi becomes '1', a data DI and an opposite phase DI are supplied to nodes N3, N4 through clocked inverters 171, 172 (data transfer gates), respectively. When a clock signal of an opposite phase becomes '1', the potential of the nodes N3, N4 are amplified and latched by clocked inverters 181, 182 (clocked gates). In this case, even if a circuit threshold value of the inverters 171, 172 is varied, these nodes N3, N4 are corrected to a correct potential immediately by the inverters 181, 182, if a magnitude relation of the potential of the nodes N3, N4 is correct. In this way, a high speed operation can be executed.

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Patent

Semiconductor Integrated circuit

Yutaka Shinagawa, +5 more
TL;DR: In this article, a semiconductor integrated circuit (SIC) has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the SIC.
Patent

Flip-flop circuit

Makoto Shikata, +3 more
TL;DR: A flip-flop circuit is a circuit composed of two basic flipflop circuits, four field effect transistors, and four amplifiers as discussed by the authors, and it is composed of a first and a second inverter circuit.
Patent

D-type flipflop

Ulf Tohsche
TL;DR: In this article, a flipflop has a first holding element with a first feedback loop and a second holding element having a second feedback loop, where the first and second feedback loops each have a first node and second node, respectively.
Patent

Latch circuit for SRAM, has four or more invertors connected in loop form

Hideo Akiyoshi
TL;DR: In this paper, a Latch circuit holding a signal temporarily, contains four or more invertors (1-4) connected in loop form, is defined, where the invertor is connected in a loop.
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Patent

Multi-input latch circuit

Yamazaki Akihiro
TL;DR: In this article, the authors propose to use a writing clock (timing signal) to a control clock of a feedback loop with no intervention of a control gate, which can reduce the pattern area ratio of an integrated circuit with improvement of integration degree.