Journal ArticleDOI
Logic design verification via test generation
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A method for logic design verification is introduced in which a gate-level implementation of a circuit is compared with a functional-level specification and it is shown that the class of design errors that can be detected is very large.Abstract:
A method for logic design verification is introduced in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test patterns that were developed to detect single stuck-line faults in the gate-level implementation are used instead to compare the gate-level implementation with the functional-level specification. In the presence of certain hypothesized design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. It is shown that the class of design errors that can be detected in this way is very large. >read more
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Correct Hardware Design and Verification Methods
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Native mode functional test generation for processors with applications to self test and design validation
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References
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Journal ArticleDOI
Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits
TL;DR: Two algorithms are presented: one, DALG-II, computes a test to detect a failure in acyclic logic circuits; the other, TEST-DETECT, ascertains all failures detected by a given test.
Book
Automated reasoning: Introduction and applications
TL;DR: This book explains what automated reasoning is and what it can do and then demonstrates how to use it to solve complex problems with applications in logic circuit design, circuit validation, real-time system design and expert systems.
Journal ArticleDOI
Diagnosis and reliable design of digital systems
TL;DR: It's coming again, the new collection that this site has, and the favorite diagnosis and reliable design of digital systems book is offered as the choice today.
Proceedings ArticleDOI
Bristle Blocks: A Silicon Compiler
TL;DR: The Bristle Block system is an attempt to create a silicon compiler that will perform the majority of the implementation computation while placing a minimum set of constraints on the designer.
Proceedings ArticleDOI
Symbolic Manipulation of Boolean Functions Using a Graphical Representation
TL;DR: A data structure for representing Boolean functions and an associated set of manipulation algorithms represented by directed, acyclic graphs in a manner similar to the representations of Lee and Akers, but with further restrictions on the ordering of decision variables in the graph.