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Open AccessProceedings ArticleDOI

Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security

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TLDR
To achieve the safety of fat pointers without increasing program state, this work compactly encode approximate base and bound pointers along with exact address pointers for a 46b address space into one 64-bit word with a worst-case memory overhead of 3%.
Abstract
Referencing outside the bounds of an array or buffer is a common source of bugs and security vulnerabilities in today's software. We can enforce spatial safety and eliminate these violations by inseparably associating bounds with every pointer (fat pointer) and checking these bounds on every memory access. By further adding hardware-managed tags to the pointer, we make them unforgeable. This, in turn, allows the pointers to be used as capabilities to facilitate fine-grained access control and fast security domain crossing. Dedicated checking hardware runs in parallel with the processor's normal datapath so that the checks do not slow down processor operation (0% runtime overhead). To achieve the safety of fat pointers without increasing program state, we compactly encode approximate base and bound pointers along with exact address pointers for a 46b address space into one 64-bit word with a worst-case memory overhead of 3%. We develop gate-level implementations of the logic for updating and validating these compact fat pointers and show that the hardware requirements are low and the critical paths for common operations are smaller than processor ALU operations. Specifically, we show that the fat-pointer check and update operations can run in a 4 ns clock cycle on a Virtex 6 (40nm) implementation while only using 1100 6-LUTs or about the area of a double-precision, floating-point adder.

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Citations
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Journal ArticleDOI

The CHERI capability model: revisiting RISC in an age of risk

TL;DR: CHERI, a hybrid capability model that extends the 64-bit MIPS ISA with byte-granularity memory protection, is presented, demonstrating that it enables language memory model enforcement and fault isolation in hardware rather than software, and that the CHERI mechanisms are easily adopted by existing programs for efficient in-program memory safety.
Proceedings ArticleDOI

Control Jujutsu: On the Weaknesses of Fine-Grained Control Flow Integrity

TL;DR: It is shown that many popular code bases such as Apache and Nginx use coding practices that create flexibility in their intended control flow graph (CFG) even when a strong static analyzer is used to construct the CFG, which allows an attacker to gain control of the execution while strictly adhering to a fine-grained CFI.
Proceedings ArticleDOI

CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization

TL;DR: This work demonstrates multiple orders-of-magnitude improvement in scalability, simplified programmability, and resulting tangible security benefits as compared to compartmentalization based on pure Memory-Management Unit (MMU) designs.
Proceedings ArticleDOI

Missing the Point(er): On the Effectiveness of Code Pointer Integrity

TL;DR: It is shown that, for architectures that do not support segmentation in which CPI relies on information hiding, CPI's safe region can be leaked and then maliciously modified by using data pointer overwrites.
Proceedings ArticleDOI

SGXBOUNDS: Memory Safety for Shielded Execution

TL;DR: SGXBounds is an efficient memory-safety approach for shielded execution exploiting the architectural features of Intel SGX based on the LLVM compiler framework targeting unmodified multithreaded applications and has performance and memory overheads similar to AddressSanitizer and Intel MPX.
References
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Proceedings ArticleDOI

Exploring security vulnerabilities by exploiting buffer overflow using the MIPS ISA

TL;DR: An example will be described using C and the MIPS assembly language that simultaneously exposes students to issues in computer security, operating systems concepts such as memory management and function invocation/return, and theMIPS instruction set architecture.
Proceedings ArticleDOI

RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks

TL;DR: RotoRouter addresses Denial-of-Service (DoS) attacks on networks with a novel protocol and router implementation that scales to port speeds in excess of 10 Gbps and links with more than 10,000 active flows.