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Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security

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TLDR
To achieve the safety of fat pointers without increasing program state, this work compactly encode approximate base and bound pointers along with exact address pointers for a 46b address space into one 64-bit word with a worst-case memory overhead of 3%.
Abstract
Referencing outside the bounds of an array or buffer is a common source of bugs and security vulnerabilities in today's software. We can enforce spatial safety and eliminate these violations by inseparably associating bounds with every pointer (fat pointer) and checking these bounds on every memory access. By further adding hardware-managed tags to the pointer, we make them unforgeable. This, in turn, allows the pointers to be used as capabilities to facilitate fine-grained access control and fast security domain crossing. Dedicated checking hardware runs in parallel with the processor's normal datapath so that the checks do not slow down processor operation (0% runtime overhead). To achieve the safety of fat pointers without increasing program state, we compactly encode approximate base and bound pointers along with exact address pointers for a 46b address space into one 64-bit word with a worst-case memory overhead of 3%. We develop gate-level implementations of the logic for updating and validating these compact fat pointers and show that the hardware requirements are low and the critical paths for common operations are smaller than processor ALU operations. Specifically, we show that the fat-pointer check and update operations can run in a 4 ns clock cycle on a Virtex 6 (40nm) implementation while only using 1100 6-LUTs or about the area of a double-precision, floating-point adder.

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Citations
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Proceedings ArticleDOI

In-fat pointer: hardware-assisted tagged-pointer spatial memory safety defense with subobject granularity protection

TL;DR: In-Fat Pointer as mentioned in this paper improves the protection granularity of tagged-pointer schemes using object metadata, which is efficient and binary-compatible for object-bound spatial safety, and uses three complementary object metadata schemes to reduce the number of pointer tag bits needed for metadata lookup.
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Rethinking the memory hierarchy for modern languages

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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 6)

TL;DR: The Capability Hardware Enhanced RISC Instructions (CHERI) instruction set architecture as discussed by the authors has been developed by SRI International and the University of Cambridge to address known performance and robustness gaps in commodity ISAs.
Proceedings ArticleDOI

FRAMER: a tagged-pointer capability system with memory safety applications

TL;DR: FRAMER improves over previous solutions by simultaneously providing a novel encoding that derives the location of per-object metadata with low memory overhead and without any assumption of objects' alignment or size, offering flexibility in metadata placement and size, and avoiding internal object memory layout changes.
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