Low Power Adder Based Digital Filter for QRS Detector
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TLDR
Low power concept of transistor stacking to reduce leakage power is introduced; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented.Abstract:
Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.read more
Citations
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Proceedings Article
A +/- 6ms-Accuracy, 0.68mm(2) and 2.21 mu W QRS Detection ASIC
Hui-Min Wang,You-Liang Lai,Mark C. Hou,Shih-Hsiang Lin,Brad S. Yen,Yu-Chieh Huang,Lei-Chun Chou,Shao-You Hsu,Sheng-Chieh Huang,Ming-Yie Jan +9 more
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Low Power Adder based ANN
S N Prasad,S. Y. Kulkarni +1 more
TL;DR: Digital implemented neural models processing element – adder with low power consumption is proposed for real-time multimedia applications and is illustrated in the 23-1 tree layer artificial neural network (ANN).
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Low Power Heterogeneous Adder
TL;DR: Low power heterogeneous adder architecture is proposed to enable flexibility to the computing applications and consume less power, and to select required quality metrics viz., area, timing and power for the design.
References
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Intra-body communication for biomedical sensor networks
TL;DR: The first VLSI implementation of a modified SPIHT algorithm offers compression ratios of up to 20:1 for ECG signals still containing all significant details for medical diagnosis and the implementations fulfill all biomedical requirements on galvanic coupling into and within the human body.
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Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits
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Journal ArticleDOI
A ±6ms-accuracy, 0.68mm2, and 2.21 µW QRS detection ASIC
TL;DR: A state-of-the-art QRS detection algorithm was modified and implemented, and the novel ASIC is proposed with 2.21 μW power consumption and 0.68mm2 core area, which is the smallest Q RS detection ASIC so far in the world.
Proceedings ArticleDOI
A ±6ms-accuracy, 0.68mm 2 and 2.21μW QRS detection ASIC
Hui-Min Wang,You-Liang Lai,Mark C. Hou,Shih-Hsiang Lin,Brad S. Yen,Yu-Chieh Huang,Lei-Chun Chou,Shao-You Hsu,Sheng-Chieh Huang,Ming-Yie Jan +9 more
TL;DR: A state-of-the-art QRS detection algorithm was modified and implemented, and the novel ASIC is proposed with 2.21 μW power consumption and 0.68mm2 core area, which is the smallest Q RS detection ASIC so far in the world.
Proceedings ArticleDOI
Ultra-low-energy near-threshold biomedical signal processor for versatile wireless health monitoring
TL;DR: An ultra-low-energy biomedical signal processor (BSP) is proposed for wireless multi-channel physiological signal monitoring that integrates a RISC core and application-specific hardware accelerators (ASHAs) to achieve ultra low power consumption while meeting required performance.