Proceedings ArticleDOI
Low power optimization technique for BDD mapped circuits
Per Lindgren,Mikael Kerttu,Mitch Thornton,Rolf Drechsler +3 more
- pp 615-621
Reads0
Chats0
TLDR
A technique for minimizing the overall sum of switching probabilities is presented and the resulting circuit that is obtained by mapping the BDD to CMOS Pass Transistors has in simulation using a commercially available process model) shown reduced power dissipation characteristic.Abstract:
The minimization of power consumption is an important design constraint for circuits used in portable devices. The switching activity of a circuit node in a CMOS digital circuit directly contributes to overall power dissipation. By approximating the switching activity of circuit nodes as internal switching probabilities in binary decision diagrams (BDDs), it is possible to estimate the dynamic power dissipation characteristic of circuits resulting from a structural mapping of a BDD. A technique for minimizing the overall sum of switching probabilities is presented. The method is based on efficient local operations on a BDD representing the functionality of the circuit to be realized. The resulting circuit that is obtained by mapping the BDD to CMOS pass transistors has in simulation (using a commercially available process model) shown reduced power dissipation characteristic. Experimental results on a set of MCNC benchmarks are given for this technique.read more
Citations
More filters
Proceedings ArticleDOI
Exact lower bound for the number of switches in series to implement a combinational logic cell
TL;DR: This paper addresses the question of how many serial switches are necessary to implement a given logic function as a switch network and proposes a design methodology that produces cells with minimum number of transistors in series and evaluates the benefits obtained in circuit delay.
Journal ArticleDOI
Teaching low-power electronic design in electrical and computer engineering
Jiann-Shiun Yuan,Jia Di +1 more
TL;DR: This work introduces several fundamental low-power design techniques and provides some examples to help students understand design methodologies.
Proceedings ArticleDOI
A comparative study of CMOS gates with minimum transistor stacks
Leomar S. da Rosa,Andre I. Reis,Renato P. Ribas,Felipe de Souza Marques,Felipe Ribeiro Schneider +4 more
TL;DR: Two approaches presenting the minimum number of stacked devices are compared, using conventional series-parallel CMOS as a reference, and takes into consideration different lists of cells, including standard cell libraries used in regular (fixed library) technology mapping or functions generated by software in library-free technology mapping.
Proceedings ArticleDOI
Power-aware FPGA logic synthesis using binary decision diagrams
TL;DR: This work presents a power-aware logic optimization tool that is specialized to facilitate subsequent power- aware technology mapping and a synthesis framework that uses binary decision diagram based collapsing and decomposition techniques in conjunction with signal switching estimates to achieve power-efficient circuit networks.
Proceedings ArticleDOI
Fast disjoint transistor networks from BDDs
Leomar S. Da Rosa Junior,Felipe de Souza Marques,Tiago M. G. Cardoso,Renato P. Ribas,Sachin S. Sapatnekar,Andre I. Reis +5 more
TL;DR: The use of disjoint pull-up and pull-down planes allows simplifications that result in shorter pull- up andPull-down transistor stacks, which leads to the fastest implementation among the six different strategies evaluated to generate transistor networks from BDDs.
References
More filters
Journal ArticleDOI
Graph-Based Algorithms for Boolean Function Manipulation
TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
Journal ArticleDOI
Binary Decision Diagrams
TL;DR: This paper describes a method for defining, analyzing, testing, and implementing large digital functions by means of a binary decision diagram that provides a complete, concise, "implementation-free" description of the digital functions involved.
Proceedings ArticleDOI
Efficient implementation of a BDD package
TL;DR: A package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation is described, based on an efficient implementation of the if-then-else (ITE) operator.
Proceedings ArticleDOI
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
TL;DR: This paper describes a technique of more efficient Boolean function manipulation that uses Shared Binary Decision Diagrams (SBDD's) with attributed edges and implements include an ordering algorithm of input variables and a method of handling don't care.
Proceedings ArticleDOI
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
Srinivas Devadas,Sharad Malik +1 more
TL;DR: This work surveys state-of-the-art optimization methods that target low power dissipation in VLSI circuits and considers the circuit, logic, architectural and system levels.