Managing performance vs. accuracy trade-offs with loop perforation
Stelios Sidiroglou-Douskos,Sasa Misailovic,Henry Hoffmann,Martin Rinard +3 more
- pp 124-134
Reads0
Chats0
TLDR
The results indicate that, for a range of applications, this approach typically delivers performance increases of over a factor of two (and up to a factors of seven) while changing the result that the application produces by less than 10%.Abstract:
Many modern computations (such as video and audio encoders, Monte Carlo simulations, and machine learning algorithms) are designed to trade off accuracy in return for increased performance. To date, such computations typically use ad-hoc, domain-specific techniques developed specifically for the computation at hand. Loop perforation provides a general technique to trade accuracy for performance by transforming loops to execute a subset of their iterations. A criticality testing phase filters out critical loops (whose perforation produces unacceptable behavior) to identify tunable loops (whose perforation produces more efficient and still acceptably accurate computations). A perforation space exploration algorithm perforates combinations of tunable loops to find Pareto-optimal perforation policies. Our results indicate that, for a range of applications, this approach typically delivers performance increases of over a factor of two (and up to a factor of seven) while changing the result that the application produces by less than 10%.read more
Citations
More filters
Journal ArticleDOI
Approximate Computing: A Survey of Recent Trends—Bringing Greenness to Computing and Communication
TL;DR: A comprehensive and concise survey of the current research trends and contributions in energy-efficient computing from computational point of view is presented.
Journal ArticleDOI
Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software
TL;DR: It is found that parallel architectures and parallelism in general provide the best means to combat and exploit variability to design resilient and efficient systems.
Proceedings ArticleDOI
Bolt: on-demand infinite loop escape in unmodified binaries
TL;DR: Bolt is a novel system for escaping from infinite and long-running loops that can detect and escape from loops in off-the-shelf software, without available source code, and with no overhead in standard production use.
Proceedings ArticleDOI
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications
Kaushik Roy,Anand Raghunathan +1 more
TL;DR: Different approaches that are developed to implement approximate hardware for error resilient applications are described and it is evident that the tradeoffs may allow approximate computing to handle tasks beyond what the authors can do with traditional computing.
Journal ArticleDOI
Approximate Logic Synthesis: A Survey
TL;DR: This work reviews methods devised to synthesize approximate circuits, given their exact functionality and an approximability threshold, and summarizes strategies for evaluating the error that circuit simplification can induce on the output, which guides synthesis techniques in choosing the circuit transformations that lead to a given amount of induced error.
References
More filters
Proceedings ArticleDOI
LLVM: a compilation framework for lifelong program analysis & transformation
Chris Lattner,Vikram Adve +1 more
TL;DR: The design of the LLVM representation and compiler framework is evaluated in three ways: the size and effectiveness of the representation, including the type information it provides; compiler performance for several interprocedural problems; and illustrative examples of the benefits LLVM provides for several challenging compiler problems.
Journal ArticleDOI
The JPEG still picture compression standard
TL;DR: The Baseline method has been by far the most widely implemented JPEG method to date, and is sufficient in its own right for a large number of applications.
Proceedings ArticleDOI
The PARSEC benchmark suite: characterization and architectural implications
TL;DR: This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs), and shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic.
Related Papers (5)
Green: a framework for supporting energy-conscious programming using controlled approximation
Woongki Baek,Trishul Chilimbi +1 more