Patent
Method and apparatus for a scannable hybrid flip flop
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TLDR
In this paper, a scannable register can be formed from a 2:1 input multiplexer, a first latch and a second latch, which can be used to test LSSD testable integrated circuits.Abstract:
A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.read more
Citations
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References
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Patent
System for scan testing of logic circuit networks
TL;DR: In this paper, the integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation.
Patent
Multiplexed-access scan testable integrated circuit
Patrick P. Fasang,John Paul Shen +1 more
TL;DR: In this paper, a testable integrated circuit contains additional circuitry which defines a plurality of scan paths in each of which are connected in series by bistable elements (specifically, special scan path flip-flops) isolated from the integrated circuit combinational circuits.
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Temporally redundant latch for preventing single event disruptions in sequential integrated circuits
D.G. Mavis,P.H. Eaton +1 more
TL;DR: In this article, a temporally redundant latch for use in integrated circuit (IC) devices redundantly samples data output from logic or other circuitry at multiple time-shifted periods to provide multiple, independent data samples from which a correct data sample can be selected.
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Testable programmable gate array and associated LSSD/deterministic test methodology
Beebe Wayne Kevin,Botala Sally,Scott Whitney Gould,Frank Ray Keyser,Larsen Wendell Ray,Palmer Ronald Raymond,Brian A. Worth +6 more
TL;DR: In this paper, a programmable gate array includes test subsystems for testing various functional subsystems of the PAG array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.
Patent
Apparatus for scannable D-flip-flop which scans test data independent of the system clock
TL;DR: The scannable-D-flip-flops as discussed by the authors can operate in a normal mode of operation or in a scan/test mode, depending on the system clock.