scispace - formally typeset
Patent

Method and apparatus for dynamically configurable multi level error correction

TLDR
In this paper, a check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal, and an error locator is configurable to produce addresses of errors in a set of data.
Abstract
An invention is provided for dynamically configurable error correction. The invention includes receiving a check code configuration signal, which indicates a particular level of error detection. A check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal. In addition, an error locator configuration signal is received that indicates a particular level of error addressing, and an error locator is configured to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.

read more

Citations
More filters
Patent

Device and method for managing die groups

TL;DR: In this article, the authors describe methods and devices that enhance the endurance of a non-volatile memory (e.g., flash memory) by obtaining, for each of the plurality of die, an endurance metric.
Patent

Mlc self-raid flash data protection scheme

TL;DR: In this paper, a two-dimensional self-RAID method is proposed to protect page-based storage data in a MLC multiple-level-cell flash memory device, which includes reserving one parity sector across each data page, reserving a parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group.
Patent

Power inrush management of storage devices

TL;DR: In this article, the authors describe systems, methods and/or devices used to enable power-inrush management of storage devices (e.g., DIMM devices), which includes, for at least one storage device populated in a slot of a plurality of storage device slots, the plurality of slots configured to be populated by two or more storage devices.
Patent

Flash storage controller execute loop

TL;DR: In this article, a storage controller is coupled with a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, with each flash port comprising an associated processor.
Patent

Flash memory controller garbage collection operations performed independently in multiple flash memory groups

TL;DR: In this article, a flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group, for each group the controller independently determines the amount of free space and performs garbage collection operation if the amount falls below a threshold.
References
More filters
Patent

Decoding a received BCH encoded signal

TL;DR: In this article, the decoding process of a BCH encoded signal is continued by determining whether the error is correctable and correcting the information contained in the bit locations of the encoded signal having the error when the identifying of bit locations is ceased.
Patent

Variable strength ECC

TL;DR: In this paper, the authors describe data detection and correction in memory controllers, memory systems, and/or non-volatile memory devices by allowing the number of ECC check bytes being utilized to be varied to increase or decrease the ECC coverage.
Patent

Data protection system

TL;DR: In this paper, the authors present systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format, and they also provide methods for protecting data stored on data storage Medium so that the data may be recovered without errors.
Patent

Error control system

TL;DR: In this paper, the authors proposed a method to perform error correction which allows information transmission requiring real-time processing by providing each of the transmission side and the reception side with a means which adds information for retransmission to each time slot and a retransmissions time limiting means which handles information retransmitted within a certain time out of erroneous information as an information signal.
Patent

Forward error corrector

TL;DR: A method for decoding an algebraic-coded message including determining a discrepancy indicator, determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected and producing a perceptible indication of the detected uncorrectability message.