Patent
Method and apparatus for efficiently handling temporarily cacheable data
John H. Anthony,William C. Brantley,Kevin P. McAuliffe,Vern Alan Norton,Gregory Francis Pfister +4 more
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TLDR
In this article, a method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data is presented, where a bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved.Abstract:
A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data. When an "invalidate marked data" instruction is received, the cache controls sweep through the entire cache directory and invalidate any cache line which has the "marked data bit" set in a single pass. An extension of the invention involves using a multi-bit field rather than a single bit to provide a more versatile control of the temporary cacheability of data.read more
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References
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Patent
Memory back-up system
TL;DR: In this article, a non-write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element, and at a context switch, the stored information is sequentially written to two separate main memory units.
Patent
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TL;DR: In this article, a tightly coupled computer system which provides for data coherency and includes an addressable main memory for storing blocks of data, a plurality of processors for accessing the blocks and a bus for intercoupling each of the plurality of processor with the main memory and with any other of the processors is presented.
Journal ArticleDOI
Effects of Cache Coherency in Multiprocessors
TL;DR: In this article, an analytical model for the program behavior of a multitasked system is introduced, including the behavior of each process and the interactions between processes with regard to the sharing of data blocks.
Patent
Cache locking controls in a multiprocessor
TL;DR: In this paper, a lock array is provided with bit positions corresponding to each line entry in an associated cache directory, and a replacement selection circuit is used to eliminate each locked line from being a replacement candidate in its congruence class in a set-associative store-in-cache in a multiprocessor (MP).
Patent
Cache store clearing operation for multiprocessor mode
Couleur J,Lange R,Pine D +2 more
TL;DR: In this article, the cache store is cleared by resetting tag directory indicators, a round robin counter and a column full flag, for each column in a four level set associative tag directory to the cache.