Patent
Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator
Erik Hogl,Ulrich Fiedler +1 more
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TLDR
In this paper, a method for synchronizing multiple subsystems using one voltage-controlled oscillator was proposed, which includes transmitting a phase and frequency aligned output of a voltage controller oscillator to each subsystem within a digital system.Abstract:
A method for synchronizing multiple subsystems using one voltage-controlled oscillator. The method includes transmitting a phase and frequency aligned output of a voltage-controlled oscillator to each subsystem within a digital system. A first subsystem of the multiple subsystems generates a first internal clock and outputs a synchronization signal to each of the other subsystems. The synchronization signal has a marker that defines a known point in time of the first internal clock. The other subsystems sample the synchronization signal using the output signal of the voltage controller oscillator to determine a starting indicator that indicates the known point in time of the first internal clock. Upon detection of the marker in the synchronization signal, the other subsystems starts a second internal clock that is synchronized with the first internal clock.read more
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References
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Patent
Digital phase alignment and integrated multichannel transceiver employing same
TL;DR: In this paper, a synchronizer and phase aligning method that provides signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc.
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Noboru Masuda,Ryotaro Kamikawai,Masayoshi Yagyu,Masakazu Hitachi Suzuki Shinden Shataku Yamamoto,Hiroyuki Itoh,Tatsuya Saito +5 more
TL;DR: In this paper, a clock signal supply system provides an adjusting circuit to adjust the phase of the received clock signals at each location where the clock signal is to be received, and this adjustment is carried out at each of the locations at which the clock signals are to be transmitted.
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Method and apparatus for clock and data recovery with high jitter tolerance
TL;DR: In this paper, an integrated phase-locked loop extracts a clock signal embedded in a data stream and a triple sampler captures jittering data and aligns them with the recovered clock.
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Large scale integrated circuit configured to eliminate clock signal skew effects
TL;DR: In this article, a clock signal supply circuit is used to supply a signal to each of a plurality of outer regions of the integrated circuit disposed around the central region, for reducing clock signal skew effects.