Patent
Method and structure for self aligned formation of a gate polysilicon layer
Reads0
Chats0
TLDR
In this article, the authors proposed a method for processing semiconductor devices that includes providing a semiconductor substrate, which includes forming a pad oxide layer over the substrate and forming a silicon nitride layer over it.Abstract:
A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon nitride layer and extends into a depth of the semiconductor substrate. The method also includes filling the trench region with an oxide material. The oxide material extends from a bottom portion of the trench region to an upper surface of the silicon nitride layer. The method includes planarizing the oxide material and selectively removing the silicon nitride layer to form an isolation structure. A polysilicon material is deposited overlying the isolation structure. The polysilicon material is planarized to expose a top portion of the isolation structure and form a first electrode and a second electrode structures separated by a portion of the isolation structure.read more
Citations
More filters
Patent
Semiconductor processing system and methods using capacitively coupled plasma
Jang-Gyoo Yang,Matthew L. Miller,Xinglong Chen,Kien N. Chuc,Qiwei Liang,Shankar Venkataraman,Dmitry Lubomirsky +6 more
TL;DR: In this paper, a capacitively coupled plasma (CCP) unit is described inside a process chamber, and a pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.
Patent
Semiconductor processing systems having multiple plasma configurations
TL;DR: In this paper, the authors describe a system that includes a first plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access.
Patent
Methods for etch of metal and metal-oxide films
TL;DR: In this paper, a method of selectively etching a metal-containing film from a substrate comprising a metal containing layer and a silicon oxide layer is proposed, which involves flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorinecontaining gas to generate a plasma in the plasma generation area.
Patent
Methods for etch of sin films
TL;DR: In this paper, a method of selectively etching silicon nitride from a substrate comprising a silicon oxide layer and a silicon dioxide layer is proposed. But the method requires the substrate to be exposed to the reactive gas in the gas reaction region of the substrate processing chamber.
Patent
Processing systems and methods for halide scavenging
Anchuan Wang,Xinglong Chen,Zihui Li,Hiroshi Hamana,Zhijun Chen,Ching-Mei Hsu,Jiayin Huang,Nitin K. Ingle,Dmitry Lubomirsky,Shankar Venkataraman,Randhir Thakur +10 more
TL;DR: In this article, a system, chambers, and processes are provided for controlling process defects caused by moisture contamination in a vacuum or controlled environment, and the chambers may include configurations to provide additional processing capabilities in combination chamber designs.
References
More filters
Patent
Methods of fabbricating a stack-gate non-volatile memory device and its contactless memory arrays
TL;DR: In this article, a stack-gate nonvolatile memory device with a tapered floating-gate structure is proposed, which offers a longer effective channel length to alleviate the punch-through effect and a larger surface area for erasing or programming between the tapered FLG structure and the integrated common-source/drain conductive structure.
Patent
Dummy structures that protect circuit elements during polishing
Hsing Ti Tuan,Chung Wai Leung +1 more
TL;DR: In this article, the authors describe how circuit elements (e.g., transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.
Patent
Method for planarized self-aligned floating gate to isolation
TL;DR: In this paper, a method for forming floating gate regions in nonvolatile memory cells each having a floating gate and a control gate is disclosed, where a plurality of isolation structures in a substrate extending above and below a surface of the substrate is formed.
Patent
Low cost and low dishing slurry for polysilicon cmp
Sen-Hou Ko,Kevin Song +1 more
TL;DR: In this paper, the authors provide methods of using compositions comprising an abrasive selected from the group consisting of alumina and ceria and a surfactant for chemical mechanical planarization of substrates to remove polysilicon.
Patent
Self-aligned gate formation using polysilicon polish with peripheral protective layer
TL;DR: In this article, a method of protecting a peripheral region, by forming a protective mask over the peripheral area, during polysilicon polishing while forming self-aligned poly-silicon gates in flash memory circuits, is presented.