Patent
Method for analyzing manufacturing test pattern coverage of critical delay circuit paths
TLDR
In this paper, an efficient method for automatically verifying test patterns devised to detect speed critical faults in electrical circuits, with minimal human intervention, is presented, which provides a controlled momentary inversion of a logic value at a control point within the circuit being tested or simulated, and then checks the measured or simulated circuit's output value.Abstract:
An efficient method is presented for automatically verifying test patterns devised to detect speed critical faults in electrical circuits, with minimal human intervention. The method provides a controlled momentary inversion of a logic value at a control point within the circuit being tested or simulated, and then checks the measured or simulated circuit's output value. If the momentary logic inversion causes an inverted logic output, then the test pattern under evaluation has been determined to be capable of detecting circuits that have failures due to speed critical problems. With such an arrangement it is possible to determine whether specific test patterns will accurately measure the performance of circuit paths that have potential operating speed related problems.read more
Citations
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Patent
System and method to facilitate evaluation of integrated circuits through delay testing
TL;DR: In this article, a set of critical paths are determined for a design associated with the IC chip, at least some of which critical paths were based on timing characteristics for the design (e.g., timing margin or slack).
Patent
IC chip at-functional-speed testing with process coverage evaluation
Eric A. Foreman,Gary D. Grise,Peter A. Habitz,Vikram Iyengar,David E. Lackey,Chandramouli Visweswariah,Jinjun Xiong,Vladimir Zolotov +7 more
TL;DR: In this paper, a statistical static timing analysis (SSTA) of a full IC chip design is described, and a process coverage is calculated for evaluation from the SSTA runnings; a particular IC chip is evaluated based on the process coverage.
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Obfuscated source program, source program conversion method and apparatus, and source conversion program
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Method for verifying and improving run-time of a memory test
TL;DR: In this article, a method of generating and verifying a memory test is described, where a simulator is used to verify that the sequence of time-ordered commands complies with a set of operating constraints for the memory.
Patent
Random path delay testing methodology
Kevin William McCauley,William Vincent Huott,Mary Prilotski Kusko,Peilin Song,Richard Frank Rizzolo,Ulrich Baur,Franco Motika +6 more
TL;DR: In this article, all paths containing a logic gate in a logic circuit are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL.
References
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Patent
Bist architecture for detecting path-delay faults in a sequential circuit
TL;DR: In this article, a scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinative portion and a plurality of scan flip-flops is presented.
Patent
Testing of integrated circuits using clock bursts
Robert M Walker,Dick L Liu +1 more
TL;DR: In this paper, a general purpose ASIC tester applies test vectors to the integrated circuit under test, and the output terminals are observed to determine if the device is in the expected state (as determined by simulation) after the clock burst.
Patent
Semiconductor integrated circuit and its evaluating method
TL;DR: In this paper, a semiconductor integrated circuit and its evaluating method for easily and inexpensively performing AC testing are provided without increasing a chip size, without increasing the number of transistors.