Patent
Method for fabricating metal oxide field effect transistors
Yo Hwan Koh,Seong Min Hwang +1 more
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TLDR
In this article, a polysilicon layer is used to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask.Abstract:
A method for fabricating a metal oxide silicon field effect transistor (MOSFET) wherein a polysilicon layer is deposited over a gate oxide film serving to insulate the gate of the MOSFET from the substrate of the MOSFET. The polysilicon layer serves to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask. Accordingly, it is possible to prevent a short circuit from occurring between the semiconductor substrate and gate electrode of the MOSFET upon forming the gate electrode.read more
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Semiconductor Device and Method of Fabricating the Same
TL;DR: In this paper, an active matrix display (AMD) with pixel electrodes, gate wirings and source wires is proposed, in which pixel electrodes are arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the amount of steps.
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Method for integrated circuit fabrication using pitch multiplication
TL;DR: In this paper, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate by pitch multiplication and conventional photolithography.
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Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
TL;DR: In this article, a single spacer process for multiplying pitch by a factor greater than two is provided, where tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrees substantially parallel to one another.
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Pitch reduced patterns relative to photolithography features
Luan Tran,William T. Rericha,John K. Lee,Ramakanth Alapati,Sheron Honarkhah,Shuang Meng,Puneet Sharma,Jingyi Bai,Zhiping Yin,Paul A. Morgan,Mirzafer K. Abatchev,Gurtej S. Sandhu,D. Mark Durcan +12 more
TL;DR: In this paper, pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to create the relatively large features of a second pattern, and the combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer.
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Mask material conversion
TL;DR: In this article, a pattern of mandrels is first formed overlying a semiconductor substrate, and spacers are then formed on the sidewalls of the mandrel by depositing a blanket layer of material over the mandrells and preferentially removing spacer material from horizontal surfaces.
References
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Patent
Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
Takeshi Okazawa,Yoshiyuki Hirano +1 more
TL;DR: A metal silicide film is formed on the sides of a polycrystalline silicon layer formed on a semiconductor substrate via an insulating film, and the surface of the metal silicides film is covered by a silicon oxide film, whereby the silicon layer has a low electrical resistance and no shortcircuiting is necessary as discussed by the authors.
Patent
Method of maufacturing a semiconductor device having a low resistance gate electrode
TL;DR: In this article, a gate-patterned polysilicon layer was used as an ion-implantation mask to form source/drain regions in the semiconductor substrate, on opposite sides of the gate electrode.
Patent
Method for fabricating polycide gate MOSFET devices
Ancheor Chen,Gary Hong +1 more
TL;DR: In this paper, a method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described.
Patent
MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region
TL;DR: In this paper, a refractory metal barrier layer is provided by forming a self-aligned refractoric metal silicide layer and a two-layer selfaligned barrier is formed.
Patent
Semiconductor integrated circuit device with multiplayered wiring
TL;DR: In this paper, a semiconductor integrated circuit device capable of having a high integration density and excellent performance and a method of fabricating the semiconductor Integrated Circuit device are disclosed, where a connecting conductor for connecting gate wiring which is formed on a field oxide film and extended from the gate of a MOSFET, to the source/drain region of another MOSFLET is interposed between the gate wiring and one of two side space layers for defining the width of the gate wires.