Patent
Method for prioritizing data transfer request by comparing a latency identifier value received from an I/O device with a predetermined range of values
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TLDR
In this article, a method for controlling data transfer operations between a main memory and other devices in a computer system is described, where each of the latency identification values corresponds with a maximum time interval in which to service the respective data transfer request.Abstract:
A method is described for controlling data transfer operations between a main memory and other devices in a computer system. Data transfer request signals and associated latency identification values are received. Each of the latency identification values corresponds with a maximum time interval in which to service the respective data transfer request. The latency identification values are periodically modified and compared to indicate the current highest priority request. In the event that service of a particular requested data transfer operation must be provided imminently, priority override functionality is provided. In this way, those devices having particular latency requirements can be provided with timely access to the main memory, and need not have separately dedicated memory or buffers.read more
Citations
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References
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Patent
Peripheral component interconnect bus system having latency and shadow timers
Uri Elazar,Yehuda Peled +1 more
TL;DR: In this paper, a shadow register and shadow timer are used to allocate a time period equal to the master device's latency value to transmit data in a PCI-PCI system.
Patent
Bus arbiter including programmable request latency counters for varying arbitration priority
Larry D. Hewitt,Scott Swanstrom +1 more
TL;DR: In this paper, a computer system is provided for controlling the ownership of a bus to which a variety of both real-time and non-real time resources are coupled, including a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership.
Patent
Method and apparatus for overriding bus prioritization scheme
TL;DR: A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times is described in this article, where the outcome of the arbitration cycle is based on a corresponding priority level associated with each of the devices.
Patent
System and method for arbitrating multi-function access to a system bus
TL;DR: In this article, a bus access arbitrator for a multi-function device is disclosed, and the arbitrator includes an access counter and comparator which are used to generate a bus request disable signal.
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Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals
TL;DR: In this article, the authors present a data processing system with multiple DRAM memory modules, providing programmable memory timing through the use of a RAM within the memory controller unit of the data processing systems.