Multi-Domain Clock Skew Scheduling
Kaushik Ravindran,Andreas Kuehlmann,Ellen M. Sentovich +2 more
- pp 801-808
TLDR
This paper presents an algorithm for constrained clockskew scheduling which computes for a given number of clockingdomains the optimal phase shifts for the domains and the assignment of the individual registers to the domains.Abstract:
The application of general clock skew scheduling is practically limited due to the difficulties in implementing a wide spectrum of dedicated clock delays in a reliable manner This results in a significant limitation of the optimization potential As an alternative, the application of multiple clocking domains with dedicated phase shifts that are implemented by reliable, possibly expensive design structures can overcome these limitations and substantially increase the implementable optimization potential of clock adjustments In this paper we present an algorithm for constrained clock skew scheduling which computes for a given number of clocking domains the optimal phase shifts for the domains and the assignment of the individual registers to the domains For the within-domain latency values, the algorithm can assume a zero-skew clock delivery or apply a user-provided upper bound Our experiments demonstrate that a constrained clock skew schedule using a few clocking domains combined with small within-domain latency can reliably implement the full sequential optimization potential to date only possible with an unconstrained clock scheduleread more
Citations
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Patent
Optimizing integrated circuit design through use of sequential timing information
TL;DR: In this paper, a method for determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design is provided, wherein the critical cycles is a cycle in the design that has the highest proportionality of delay to number of registers.
Patent
Method and apparatus for circuit design and retiming
TL;DR: In this article, a data flow graph representation of the module is constructed based on the target clock period of the circuit and the correlation between the latencies and the minimum clock periods.
Proceedings ArticleDOI
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
Chuan Lin,Hai Zhou +1 more
TL;DR: This paper presents an optimal skew scheduling algorithm for sequential circuits with flip-flops, given a finite set of prescribed skew domains, that finds a domain assignment for each flipping-flop such that the clock period is minimized with possible delay padding.
Proceedings ArticleDOI
Physical placement driven by sequential timing analysis
TL;DR: This paper describes a new placement algorithm that is based on a tight integration of sequential timing analysis in the inner loop of an analytic solver, and minimizes the maximum mean delay on any circuit loop, thus enabling the full optimization potential of clock skew scheduling and in-place retiming.
Patent
Optimizing integrated circuit design through balanced combinational slack plus sequential slack
TL;DR: In this paper, a method for determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design is provided, wherein the critical cycles is a cycle in the design that has the highest proportionality of delay to number of registers.
References
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Book
Introduction to Algorithms
TL;DR: The updated new edition of the classic Introduction to Algorithms is intended primarily for use in undergraduate or graduate courses in algorithms or data structures and presents a rich variety of algorithms and covers them in considerable depth while making their design and analysis accessible to all levels of readers.
Proceedings ArticleDOI
Chaff: engineering an efficient SAT solver
TL;DR: The development of a new complete solver, Chaff, is described which achieves significant performance gains through careful engineering of all aspects of the search-especially a particularly efficient implementation of Boolean constraint propagation (BCP) and a novel low overhead decision strategy.
Proceedings ArticleDOI
Sequential circuit design using synthesis and optimization
E.M. Sentovich,K.J. Singh,Cho W. Moon,Hamid Savoj,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +5 more
TL;DR: SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits.
Optimizing synchronous systems
TL;DR: A transformation that converts synchronous systems into more time-efficient, systolic implementations by removing combinational rippling is presented, showing how the problem of determining the optimized system can be reduced to the graph-theoretic single-destination-shortest-paths problem.
Journal ArticleDOI
Clock skew optimization
TL;DR: Using a model to detect clocking hazards, two linear programs are investigated: minimizing the clock period, while avoiding clock hazards, and for a given period, maximizing the minimum safety margin against clock hazard.