Patent
Multi-state EEprom read and write circuits and techniques
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TLDR
In this article, the read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time by using a set of reference cells which closely track and make adjustment for the variations presented by memory cells.Abstract:
Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.read more
Citations
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Semiconductor device, and manufacturing method thereof
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
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TL;DR: In this paper, an electrically erasable programmable read-only memory (EEPROM) with a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed.
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References
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Patent
Highly scalable dynamic RAM cell with self-signal amplification
TL;DR: In this paper, a memory cell comprises a substrate of a first conductivity type (preferably N type) in which is formed a first region of opposite conductivities type.
Patent
Intelligent electrically programmable and electrically erasable ROM
TL;DR: In this article, an E2 PROM is disclosed which provides automatic programming verification, and the verification is conducted at potentials other than the normal reference potential to assure that the cells are well programmed with either binary zeroes or binary ones.
Journal ArticleDOI
A four-state EEPROM using floating-gate memory cells
C. Bleiker,H. Melchior +1 more
TL;DR: In this paper, an electrically erasable programmable read-only memory (EEPROM) is used in a novel way as a four-state memory by charging the floating gate to determined values.
Patent
Word-by-word electrically reprogrammable nonvolatile memory
TL;DR: In this paper, the termination of the variable durations is indicated by attainment of a predetermined erase or, respectively, write condition of one or more memory cells from the memory line to be erased or written.
Patent
Electrically programmable semiconductor memory showing redundance
TL;DR: In this paper, the memory cells of the EEPROM with respect to variations of the threshold values are checked at defined intervals and by employing a classifying circuit integrated in an EE PROM.