Journal ArticleDOI
Multi-valued circuits in fault detection of binary logic circuits☆
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TLDR
Two possibilities of employing multi-valued logic circuits for testing of binary networks are considered, the first augments binary synchronous sequential machines through the addition of permutation inputs withmulti-valued outputs and the second embeds binary combinational networks into easily testable ternary ones.About:
This article is published in Microelectronics Reliability.The article was published on 1976-01-01. It has received 7 citations till now. The article focuses on the topics: Sequential logic & Logic gate.read more
Citations
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Journal ArticleDOI
Multiple-Valued Logic—its Status and its Future
TL;DR: This tutorial/survey paper will review the historical developments in this field, both in circuit realizations and in methods of handling multiple-valued design data, and consider the present state-of-the-art and future expectations.
Journal ArticleDOI
The Prospects for Multivalued Logic: A Technology and Applications View
TL;DR: The historical and technical background of MVL, and areas of present and future application are described, intended to serve as a tutorial for the nonspecialist.
Proceedings ArticleDOI
Two decades of multiple-valued logic-an invited tutorial
TL;DR: The developments, major achievements, and disappointments of the past 20 years of multiple-valued logic are reviewed and the comprehensive bibliography is broken down by subject as well as listing proceedings and textbooks.
Journal ArticleDOI
Detection of Single, Stuck-Type Failures in Multivalued Combinational Networks
TL;DR: This paper introduces the concept of a partially enabled gate, K-paths in combinational circuits and a new notation for multivalued fault detection and a modified form of the D-algorithm is developed for fault detection inMultivalued circuits as well as a δ algorithm for the simplification of multivaluing test sets.
Journal ArticleDOI
Minimal TANT Networks of Functions with DON'T CARE'S and Some Complemented Input Variables
TL;DR: The minimization algorithm of Gimpel realizes a minimal TANT network for any Boolean function under a NAND gate cost criterion.
References
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Journal ArticleDOI
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
Stephen S. Yau,Yu-Shan Tang +1 more
TL;DR: An algorithm for generating the complete test set of each stuck-at-0 and stuck- at-1 single fault in a combinational logic circuit is presented and some ideas on the construction of test sets for detecting multiple faults based on Boolean differences are presented.
Journal ArticleDOI
Design of Sequential Machines with Fault-Detection Capabilities
Zvi Kohavi,Pierre A. Lavallee +1 more
TL;DR: A method is developed to obtain for any arbitrary sequential machine a corresponding machine which contains the original one and which is definitely diagnosable, and simple and systematic techniques are presented for the construction, and the determination of the length, of the distinguishing sequences of these machines.
Journal ArticleDOI
Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks
TL;DR: Multithreshold many-valued switching primitives are introduced and it is shown that they can be advantageously employed in large combinational networks, such as those found in arithmetic units.
Journal ArticleDOI
Sequential Machines Capable of Fault Diagnosis
TL;DR: By a checking sequence for a sequential machine, the authors mean an input-output sequence with a special property such that, when the input sequence is applied to the machine, the decision whether or not the machine operates correctly can be made by comparing the output sequence with the output of the machine.
Journal ArticleDOI
Fault Detection of Binary Sequential Machines Using R-Valued Test Machines
D.A. Sheppard,Zvonko G. Vranesic +1 more
TL;DR: An improved method for detection of faults in completely specified synchronous sequential machines is described, and heuristic optimization of additional permutation inputs is shown to lead to considerable reduction in the length of the fault sequence.