Next generation eWLB (embedded wafer level BGA) packaging

TLDR: In this paper, the authors highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin e-WLB and extra large eWLP as well as double-side with vertical interconnection.

Abstract: Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. “Fan-in” (FI)-WLP typically has a limitation to be less than 6x6mm in order to pass board level reliability requirements such as drop test and temperature cycle due to the mismatch of Si material properties to the PCB. However, the “Fan-out” (FO)-WLP, has been developed and introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. The most prominent type of FO-WLP is the eWLB technology (embedded Wafer Level Ball Grid Array). Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin eWLB and extra large eWLB as well as double-side with vertical interconnection. These key technologies of next generation eWLB enable 3D eWLB applications such as SoW (SiP on Wafer) and 3D SiP. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. The process flow of next generation eWLB fabrication, assembly and packaging challenges will be discussed. This paper will also present some of the achievements in package reliability, mechanical characterization and performance.