ETH Library
Novel Efficiency-Optimal
Frequency Modulation for High
Power Density DC/AC Converter
Systems
Conference Paper
Author(s):
Neumayr, Dominik; Bortis, Dominik ; Hatipoglu, Enes; Kolar, Johann W.; Deboy, Gerald
Publication date:
2017
Permanent link:
https://doi.org/10.3929/ethz-b-000187517
Rights / license:
In Copyright - Non-Commercial Use Permitted
Originally published in:
https://doi.org/10.1109/IFEEC.2017.7992148
This page was generated automatically upon download from the ETH Zurich Research Collection.
For more information, please consult the Terms of use.
Novel Efficiency-Optimal Frequency Modulation for
High Power Density DC/AC Converter Systems
D. Neumayr, D. Bortis, E. Hatipoglu and J. W. Kolar
Power Electronic Systems Laboratory,
ETH Zurich, Switzerland
Email: neumayr@lem.ee.ethz.ch
G. Deboy
Infineon Technologies Austria AG,
Villach, Austria
Email: Gerald.Deboy@infineon.com
Abstract—State-of-the-art high power density AC/DC and
DC/AC converter systems typically employ Triangular Current
Mode (TCM) modulation or conventional PWM. TCM is char-
acterized by a wide variation of switching frequency over the
mains period and ensures soft-switching in all operating points,
but results in increased conduction and high-frequency losses
due to the necessary large current ripple. In contrast, PWM
with constant switching frequency features a lower RMS current
and thus reduced conduction losses, but cannot achieve soft-
switching over the entire mains period and suffers from turn-on
losses. In this paper it is investigated if an optimal combination
of these two operating modes, i. e. an optimal adjustment of
switching frequency and/or current ripple amplitude throughout
the mains period, can lead to an increase in conversion efficiency
and how such an Optimal Frequency Modulation (OFM) control
scheme can be implemented in practice. The presented analysis is
based on an ultra compact 2kW, 400V DC/AC converter system
designed to overcome the GOOGLE Little Box Challenge.
Index Terms—Optimal Frequency Modulation, Efficiency Op-
timal Switching Frequency, Optimal Current Ripple Modulation,
Minimum Loss Control
I. INTRODUCTION
In kW-scale high power density AC/DC and DC/AC con-
verter systems, typically a high switching frequency is selected
in order to ensure a small size of the passive components [1].
As a consequence, Zero Voltage Switching (ZVS) of the power
semiconductors over the entire mains period is desired to re-
duce switching losses and keep the conversion efficiency high
and the volume of the cooling system small. Following this
design philosophy, and with the insights gained from Pareto
optimization results, a 8.2 kW/dm
3
(134 W/in
3
) single-phase
Triangular Current Mode (TCM) PV inverter was realized in
[2] to overcome the GOOGLE Little Box Challenge (GLBC)
[3]. Further research conducted in the aftermath of the GLBC
revealed that by means of an alternative inverter topology
based on a DC/|AC| buck-stage with subsequent |AC|/AC
unfolder (cf. Fig. 1) the power density of the 2 kW PV inverter
can be further improved. The buck-stage, highlighted in light
blue in Fig. 1, is operated either with TCM modulation or
conventional PWM with large current ripple, and is controlled
such that the output voltage v
C0
follows a rectified sinusoidal
shape. In order to deal with reactive loads and retain full
controllability of the inductor current, v
C0
is actually kept
above a defined voltage v
C0,min
around the Zero Crossings
(ZC) of the mains voltage as indicated in Fig. 1 (b). During
this interval, the |AC|/AC unfolder initiates PWM operation
in order to ensure a sinusoidal shape of v
ac
at the converter
output. The Pareto optimization presented in [2] identified
that if the buck-stage is operated with PWM at EMI friendly
140 kHz and a 50 µH inductor is installed, a staggering power
density of 14.7 kW/dm
3
(241 W/in
3
) at 98.1 % efficiency
can be expected. Interestingly, TCM operation of the buck-
stage with a 10 µH inductor results in a slightly lower power
density (14.0 kW/dm
3
). The resulting inductor current i
L
and switching frequency variation over a mains period for
the PWM and TCM design of the buck-stage are shown in
Fig. 2 (a) and (b) for a 2 kW ohmic load. As it becomes
evident from Fig. 2 (a), PWM features lower conduction and
winding losses due to the comparably small current ripple and
thus lower RMS value of the inductor current. However, a
hard turn-on of the high-side transistor over a wide range of
the mains period results in high switching losses. Regarding
efficiency it might be beneficial to lower f
s
between
1
/8T
m
and
3
/8T
m
in order to increase the current ripple and extend
the region where ZVS applies. On the contrary, operation of
the buck-stage with TCM modulation as shown in Fig. 2 (b)
enables ZVS in all operating points throughout mains period,
but the large current ripple significantly increases conduction
and winding losses. In this case, it might be beneficial, in
terms of overall efficiency, to limit the drop of f
s
around
the peak of the mains voltage (at
1
/4T
m
and
3
/4T
m
) in order
to decrease the current ripple despite ZVS is intermittently
lost. Accordingly, the question arises, whether the benefits of
TCM and PWM can be combined, if the switching frequency
variation is considered as an additional degree of freedom
to effectively minimize the power loss in the inverter at
every instant in time over the course of the mains period. In
[4] an optimal switching frequency for a full-bridge inverter
was derived analytically by means of a sophisticated time-
domain current ripple analysis. However, solely power losses
in the transistors due to hard switching were considered in
the optimization. The authors in [5] also included the power
loss of the inductor in the analytical optimization. However,
again, only hard-switching operation of the power transistors
was considered. The optimal variable switching frequency for
a 3-phase GaN based TCM inverter was derived in [6] based
on approximate loss models of the involved power transistor
C
DC
L
C
1
C
1
L
out
redlofnUkcuB
EMC
Filter
v
C0
L
out
C
0
v
UF
v
DC
v
AC
i
AC
i
L
i
f
+
−
+
−
t
t
v
C0
v
C0
v
C0,min
v
C0,min
-v
C0,min
v
UF
v
UF
v
C0,ref
(a) (b)
Fig. 1. (a) Inverter topology based on a DC/|AC| buck stage and a subsequent |AC|/AC full-bridge unfolder. (b) Buck stage output voltage and unfolder
output voltage showing intermediate PWM operation around the zero-crossing of the mains.
Current i
L
(A)
f
s
(kHz)
f
s
Current i
L
(A)
L = 40μH
f
s
= 140kHz
L = 10μH
f
s,min
= 50kHz f
s,max
= 580kHz
0 T
m
1/2T
m
1/4T
m
1/8T
m
3/8T
m
3/4T
m
Time
-10
10
0
20
30
-10
(a)
(b)
0
200
400
600
f
s
(kHz)
0
200
400
600
10
0
20
30
turn-on transient: soft partly-hard hard
f
s
5/8T
m
7/8T
m
Fig. 2. Inductor current i
L
and the variation of switching frequency f
s
throughout a mains period T
m
obtained for the Pareto optimal TCM and
PWM DC/|AC| buck stage when operated at rated power, respectively.
and magnetic components. However, since ZVS operation was
enforced in all operating points, the optimal trade-off between
power transistor and filter component losses has not been
completely investigated.
In this paper the optimal switching frequency variation is
determined empirically by means of experimental hardware
rather than based on mathematical loss models and simu-
lations. Since it promises highest power density, the buck-
unfolder inverter design with PWM operation of the buck stage
presented in [2] will be the basis for the study presented in
the following. In particular, the optimal switching frequency
of the buck stage (cf. Fig. 1 (a)) in order to achieve loss
minimal operation at every instant in time over the mains
period is determined. Power losses in the remaining converter
components, for instance conduction losses in the unfolder
and losses in the subsequent EMC filter are assumed to be
unaffected by the switching frequency of the buck stage and
are therefore excluded from further consideration. The reader
should be aware that EMI compliance imposes a stringent
side condition which restricts the feasible range of switching
frequency variation and/or requires a reevaluation of the EMC
filter afterwards which possibly leads to a decrease in power
density of the overall inverter. However, the EMC filter of
the buck-unfolder inverter, considered herein, is dimensioned
such to provide enough attenuation to handle the intermediate
High Frequency (HF) switching of v
C0,min
of the unfolder (cf.
Fig. 1 (b)) and therefore provides enough margin to accom-
modate for a wide range of switching frequency variation in
the DC/|AC| buck stage.
The loss minimization procedure based on switching fre-
quency variation in quasi-stationary DC/DC operating points is
outlined in Section II of this paper. The employed experimental
test setup of the buck converter is introduced afterwards
in Section III. The empirically obtained optimal switching
frequency and the resulting inductor current envelope as a
function of the point in time t
k
and/or angle considered
within a main period T
m
are presented and discussed in
Section IV. Finally, two control approaches to implement
Optimal Frequency Modulation (OFM) in practice are briefly
introduced in Section V.
II. QUASI-STATIONARY DC/DC ANALYSIS
Since the buck-stage output voltage v
C0
changes very
slowly throughout T
m
with respect to the actual switching
period T
s
=
1
/f
s
, the DC/|AC| operation of the buck con-
verter can be approximated by a large number of consecutive,
quasi-stationary DC/DC operating points defined by the DC-
link voltage, the buck stage output-voltage
v
C0
≈ max(v
C0,min
, |v
AC
(t
k
)|), (1)
and the average inductor current
i
L
= sgn (v
AC
(t
k
)) · (i
AC
(t
k
) + i
f
(t
k
)) (2)
≈ sgn (v
AC
(t
k
)) · i
AC
(t
k
) (3)
at distinct points t
k
over the mains period. Due to symmetry,
it suffices to consider only the interval ϕ = ωt = [0,
π
/2]
of the mains. In this paper, only operating points resulting
from a purely ohmic 0.25 kW, 1.0 kW and 2.0 kW load
are considered as illustrated in Fig. 3 (a). Furthermore, the
reactive current demand of the EMC filter is neglected. In a
t
t
t
k
P
v,
tot
P
v,
min
P
v,
tot
f
s,opt
f
S
f
S
f
S,1
f
S,1
< f
S,2
< f
S,3
f
S,2
f
S,3
∆i
L,opt
∆i
L,pp
i
L
,
i
L
v
C0
v
AC
v
C0
v
C0,k
fixed
V
DC
,
(a) (b) (c)
v
C0
i
L
i
L,k
i
L
12
10
8
6
4
2
0
0 50 100 150 200 250 300 350
2 kW
1 kW
0.25 kW
C
DC
L
v
C0
C
0
R
L
V
DC
i
L
i
L
+∆i
L
T
m
Fig. 3. Determining the switching frequency / current ripple which minimizes the total power loss of the DC/|AC| buck stage in a quasi-stationary DC/DC
operating point. (a) Derived DC/DC operating points V
DC
, v
C0,k
and i
L,k
for ohmic load at several distinct points t
k
throughout the mains period T
m
.
(b) Resulting current ripple amplitude for switching frequency variation in a specific DC/DC operating point. (c) Variation of the switching frequency in order
to determine the loss minimum in a given DC/DC operating point.
stationary operating point, the switching frequency of the buck
stage can be varied which results in different current ripple
amplitudes in the filter inductor L as illustrated in Fig. 3 (b).
The switching frequency f
s,opt
and current ripple amplitude
∆i
L,opt
which minimizes the total power loss in the buck stage
in the selected DC/DC operating point is considered optimal
as shown in Fig. 3 (c). After repeating the measurement
and/or optimization procedure for all defined DC/DC operating
points, the individual f
s,opt
points are joined and interpolated
in order to obtain the optimal switching frequency variation
over the course of the mains period.
The quasi-stationary DC/DC approach implicates the fol-
lowing approximations. The dielectric loss in the filter capaci-
tor C
0
due to the rectified sinusoidal voltage swing of v
c0
is not
covered by the quasi-stationary DC/DC approach. However,
these losses are in a first approximation not affected by the
switching frequency and can thus be treated as additional con-
stant power loss. The winding losses in the inductor caused by
the low-order spectral components in i
L
are also not correctly
covered, since the losses are caused solely by the DC winding
resistance, R
w,DC
, in the respective DC/DC operating point.
Since the amplitude of the harmonics of i
L
drops with
1
/n
2
and
the frequency dependent winding resistance R
w,AC
(n · f
m
) is
approximately constant up to several kHz, the resulting error is
less than 1 % as a numeric calculation revealed. Furthermore,
harmonic sidebands, present in the current spectrum due the
modulation of the rectified sinusoidal variation of the duty-
cycle during regular operation, are missing in case of the
quasi-stationary analysis even if a large number of DC/DC
operating points is considered because the duty-cycle is kept
constant during the measurements and the spectral energy
is located solely at multiples of the switching frequency.
However, since the considered switching frequency range is
much higher compared to the low-frequency harmonics in the
baseband, the additional sidebands do not noticeably affect
the losses. Moreover, the operating temperature of the power
electronic components during the individual measurements of
the quasi-stationary analysis (kept between 35
◦
C – 45
◦
C in
every considered operating point) likely differs from the device
temperature resulting from regular operation of the buck stage
50 µH
Inductor
Filter
Capacitors
Aux. Supply
CeraLink
Cooling Fan
GaN Half-Bridge
(with Heat Sink)
Fig. 4. (a) Picture of the experimental test setup showing the implemented
buck converter (GaN half-bridge with externally connected inductor) with
cooling fans and measurement probes. The employed DC source, electronic
load and power analyzer are not shown.
(max. 65
◦
C according to [3]).
III. EXPERIMENTAL SETUP
The half-bridge circuit of the buck converter (cf. Fig. 1) is
realized with normally-off gallium nitride gate (GaN) injection
transistors (CoolGaN Samples from Infineon) in combination
with a novel high-performance gate drive circuit, where two
GaN transistors are connected in parallel per switch. The
employed 50 µH HF inductor is realized with 27 turns (3
layers with each 9 turns) of 180 × 71 µm litz wire on a
RM10 N87 ferrite core. The DC-link capacitor C
DC
≈ 10 µF
is realized with individual 2 µF/650 V CeraLink capacitors
featuring exceptional low ESR at high frequencies and ele-
vated operating temperatures. It should be noted that C
DC
is dimensioned to filter switching frequency noise and not
to cope with the double-mains frequency power pulsation
intrinsic to single-phase systems. The buck stage filter ca-
pacitor C
0
≈ 20 µF is composed of 12 parallel connected
2.2 µF/450 V X6S MLCCs. As mentioned in the introduction,
the system parameters of the buck stage are in accordance with
v
sw
i
L
v
gate
f
s
= 120 kHz - Soft-Switching f
s
= 140 kHz - Partial Hard-Switching f
s
= 190 kHz - Hard-Switching
Fig. 5. Measured switch-node voltage v
sw
, inductor current i
L
and gate voltages in the DC/DC operating point V
DC
= 400 V, v
C0
= 170 V, i
L
= 5.9 A
obtained with 120 kHz, 140 kHz and 190 kHz switching frequency.
the Pareto optimal buck-unfolder inverter design presented in
[2]. The experimental test setup including cooling fans and
attached measurement probes is depicted in Fig. 4. The duty-
cycle of the half-bridge and an electronic load (Chroma 63202)
are adjusted to meet the correct output voltage and output
power (average inductor current) in every DC/DC operating
point. Depending on the specific operating point and selected
switching frequency, the rising- and falling-edge dead-time of
the half-bridge, t
d,r
, t
d,f
∈ [20 ns, 400 ns], are adapted such
to ensure a complete resonant transition of the drain-source
voltage and, in addition, minimize the conduction time of the
anti-parallel diode. In case that i
L
remains strictly positive and
hard-switching occurs, the rising-edge dead-time is set to the
minimum value. The average power loss of the buck converter
in every DC/DC operating point is measured with a Yokogawa
WT3000 power analyzer. Auxiliary power for the digital
control card and the gate drives are also included in the total
power losses. Once the operating point of the buck converter
is set, the total power loss at steady-state operation is recorded
for several switching frequencies until a distinct loss-minimum
can be identified. Fig. 5 shows experimental waveforms of
the buck converter operating at V
DC
= 400 V, v
C0
= 170 V,
i
L
= 5.9 A and switching frequencies of 120 kHz, 140 kHz
and 190 kHz. It can be seen how the triangular ripple, and
consequently the RMS value, of the inductor current reduces
with increasing switching frequency. The depicted switch-node
voltage v
sw
reveals that the power-stage experiences complete
soft-switching when operated with 120 kHz. If f
s
is increased
to 140 kHz, the slightly negative value of i
L
at the start of
the low- to high-side switching transition does not suffice to
achieve a complete resonant transition of the the switch-node
voltage for t
d,r
= 400 ns and partial hard-switching occurs.
Operating the buck converter with 190 kHz results in a hard
turn-on of the high-side transistor since i
L
remains above zero
due to the reduced amplitude of the triangular ripple. In the
DC/DC operating point examined in Fig. 5, the optimal loss
trade-off between power transistors and filter components is
attained with f
s
= 140 kHz.
IV. EMPIRICALLY DETERMINED OPTIMAL SWITCHING
FREQUENCY
Following the quasi-stationary approach, the loss-minimal
switching frequency, f
s,opt
, was determined at 10 distinct
TABLE I
FREQUENCY VARIATION AND LOSS SAVING OF OFM FOR DIFFERENT
OUTPUT POWER LEVELS
P
out
(W) f
s,OFM
P
v
(W) P
v
(W) ∆P
v
(W / %)
(kHz) @ 140 kHz @ f
s,OFM
2000 [70, 149] 24.0 20.6 3.4 / 13.7
1000 [70, 243] 10.8 8.4 2.4 / 22.0
250 [140, 500] 6.5 5.5 1.0 / 15.7
DC/DC operating points within the interval [0,
π
/2] of the
mains period for an average output power of 250 W, 1 kW
and 2 kW. The experimental results with interpolation between
the discrete measured points are shown in Fig. 6. It should
be noted that for a clearer visual representation, the mea-
sured points were mirrored at
π
/2 to complement the interval
[0, π]. The switching frequency variation and instantaneous
power loss in the buck converter when operated with a fixed
switching frequency of 140 kHz (plotted in red) and with
varying optimal switching frequency (plotted in sky-blue) are
shown in Fig. 6 (a) and (b), respectively. The corresponding
envelope of the inductor current is displayed in Fig. 6 (d)-
(f) for the three measured output power levels. At 2 kW
rated power, f
s,OFM
= f
s,opt
(ϕ) falls below 140 kHz over
a wide range of the considered phase angle. Saturation of the
power inductor limits the switching frequency to fall below
70 kHz at ωt =
π
/2. Observing the current ripple envelope
of both PWM and OFM in Fig. 6 (d), it can be inferred that
OFM tends to extend the interval where soft-switching applies
despite the increased RMS value of the inductor current.
As listed in Tab. I, the total losses in the buck converter
decrease by roughly 14 % when operating with a variable
switching frequency f
s,OFM
instead of f
s,PWM
= 140 kHz.
The loss distribution in Fig. 6 (c), calculated with experimen-
tally verified mathematical loss model of the GaN transistors
and power inductor, indicates that OFM significantly reduces
the switching and core losses while it slightly increases the
conduction and HF winding losses due to the larger current
ripple. At half the nominal output power i.e. 1 kW, the optimal
frequency curve exceeds f
s,PWM
in the vicinity of
π
/6 reaching
a peak of 243 kHz. Similar as before, the optimal frequency
drops below 140 kHz in the interval [
π
/3,
2π
/3] and reaches the
lowest value of 70 kHz at
π
/2. At 1 kW output power, 22 %
