Patent
Novel semiconductor system and device
TLDR
In this paper, a 3D IC based system including a first semiconductor layer including first alignment marks and first transistors, wherein the first transistor are interconnected by at least one metal layer including aluminum or copper, is presented.Abstract:
A 3D IC based system including: a first semiconductor layer including first alignment marks and first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer; and wherein the second transistors include a plurality of N-type transistors and P-type transistors, and wherein the second mono-crystallized semiconductor layer is transferred from a reusable donor wafer.read more
Citations
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Vertical memory devices and methods of manufacturing the same
TL;DR: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, channels arranged in vertical openings formed through at least some of the layers, and a remaining area of the portion not occupied by the conductive barrier or filling layer pattern as mentioned in this paper.
Patent
Novel semiconductor device and structure
TL;DR: In this paper, the authors consider a device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnect layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first Interconnect layer, and a connection path connecting one of the second transistor to the firstInterconnect layer.
Patent
Methods of forming nanowire devices with doped extension regions and the resulting devices
TL;DR: In this paper, a method of patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces was proposed, and after forming the doped extension regions, forming epi semiconductor materials in source and drain regions of the device.
Patent
Vertical memory devices
TL;DR: In this paper, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low-resistance layer, vertical channels on the channel layer, and a plurality of gate lines.
References
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Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
Patent
Method for forming a buried dielectric layer underneath a semiconductor fin
TL;DR: In this article, methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device are described. But the method is not suitable for the case of a single fin.
Patent
Electronic circuit device
Haruka Shimizu,Natsuki Yokoyama +1 more
TL;DR: In this article, an electronic circuit device is obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the FET.