Pipelined and Parallel Architecture of Reversible Watermarking for Greyscale Images

TLDR: A reversible watermarking strategy using prediction technique with its hardware architecture is proposed and three different architectural structures are proposed as pipelined, parallel and dataflow architecture with embedding concept.

Abstract: Background: The rapid advancement of multimedia technology has made the data communication and data sharing so comfortable through wireless network and Internet. During this multimedia communication, the piracy of the multimedia content is a primary concern (i.e. anyone can duplicate or alter the originality). One of the most efficient techniques to protect the multimedia data is watermarking. It is the process of adding a secret digital signature to the host content in a visible or invisible form. The process of watermarking will be of reversible or irreversible nature. Method: In this paper, a reversible watermarking strategy using prediction technique with its hardware architecture is proposed. In the VLSI implementation aspect three different architectural structures are proposed as pipelined, parallel and dataflow architecture with embedding concept. Findings: Finally, all the three architectural designs are modelled and implemented using Verilog HDL. The entire process is integrated in a specific chip. Application: It can be used as a separate co-processor for carrying out the watermarking in real time with any multimedia devices.