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Journal ArticleDOI

Reconfigurable accelerators for combinatorial problems

Marco Platzner
- 01 Apr 2000 - 
- Vol. 33, Iss: 4, pp 58-60
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TLDR
The authors detail the results of their prototype that results an order-of-magnitude speed-up in the execution of difficult satisfiability problems and suggest an ideal candidate for improvements based on instance-specific reconfiguration.
Abstract
Reconfigurable accelerators can improve process time on combinatorial problems with fine-grained parallelism. Such problems contain a huge number of logical operations (NOT, AND and OR) that can evaluate simultaneously, a characteristic that varies considerably from problem to problem. Because of this variability, such combinatorial problems are approached using instance-specific reconfiguration-hardware tailored to a specific algorithm and a specific set of input data. Boolean satisfiability (SAT for short) is a common combinatorial problem that exhibits fine-grained parallelism. SAT varies considerably based on the situation. Its solution is thus an ideal candidate for improvements based on instance-specific reconfiguration. In fact, simulation of an instance-specific accelerator show potential speed-ups by a factor of up to 140,000 in execution time over the solution by a software solver. The authors detail the results of their prototype that results an order-of-magnitude speed-up in the execution of difficult satisfiability problems.

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Citations
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Cancelable key-based fingerprint templates

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Journal ArticleDOI

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References
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Journal ArticleDOI

A Computing Procedure for Quantification Theory

Martin Davis, +1 more
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Proceedings ArticleDOI

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Book ChapterDOI

Acceleration of Satisfiability Algorithms by Reconfigurable Hardware

TL;DR: A design tool flow and prototype implementation of an instance-specific satisfiability solver are presented and the results prove that many of the DIMACS examples can be accelerated with current FPGA technology.
Proceedings ArticleDOI

Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment

TL;DR: This work considers reconfigurable hardware accelerators for the NP-complete Boolean satisfiability problem and integrates the advantages of an object-oriented design environment with full control over placement at every level of abstraction with commercial FSM synthesis and optimization.
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