Journal ArticleDOI
RT-level ITC'99 benchmarks and first ATPG results
TLDR
In this article, the authors propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools, such as testability evaluation of circuits and the evaluation of testability of circuits.Abstract:
New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach.read more
Citations
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Journal ArticleDOI
Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation
TL;DR: In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented, which uses FPGA emulation in an autonomous manner to fully exploit the FPGAs emulation speed.
Journal ArticleDOI
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
TL;DR: An FPGA-based approach to speed-up fault injection campaigns for the evaluation of the fault-tolerance of VLSI circuits is proposed, allowing emulating the effects of faults and observing faulty behavior.
Journal ArticleDOI
Exploiting circuit emulation for fast hardness evaluation
TL;DR: In this paper, a field-programmable gate-array based circuit emulation for performing fault-injection campaigns is proposed, which is about four orders of magnitude faster than simulation-based fault injection.
Proceedings ArticleDOI
Hardware obfuscation using PUF-based logic
James B. Wendt,Miodrag Potkonjak +1 more
TL;DR: This paper introduces the notion of PUF-based logic which can be configured to be functionally equivalent to any arbitrary design, as well as a new architecture for wire merging that obfuscates signal paths exponentially.
Proceedings ArticleDOI
FPGA technology mapping: a study of optimality
TL;DR: An algorithm is developed, based on Boolean satisfiability (SAT), that is able to map a small subcircuit into the smallest possible number of lookup tables (LUTs) needed to realize its functionality.
References
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Proceedings ArticleDOI
Combinational profiles of sequential benchmark circuits
F. Brglez,D. Bryan,K. Kozminski +2 more
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Journal ArticleDOI
Automatic generation of functional vectors using the extended finite state machine model
TL;DR: Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flip-flops can be generated automatically in a few minutes of CPU time using the prototype system.