Patent
Salvaging lock elision transactions with instructions to change execution type
Reads0
Chats0
TLDR
In this paper, a transactional memory system salvages a hardware lock elision (HLE) transaction by stopping HLE transactional execution at the point of failure in the code region.Abstract:
A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system executes a lock-acquire instruction in an HLE environment and records information about a lock elided to begin HLE transactional execution of a code region. The processor detects a pending point of failure in the code region during the HLE transactional execution. The processor stops HLE transactional execution at the point of failure in the code region. The processor acquires the lock using the information, and based on acquiring the lock, commits the speculative state of the stopped HLE transactional execution. The processor starts non-transactional execution at the point of failure in the code region.read more
Citations
More filters
Patent
Hint instruction for managing transactional aborts in transactional memory computing environments
Fadi Y. Busaba,Harold W. Cain,Dan F. Greiner,Michael K. Gschwind,Maged M. Michael,Valentina Salapura,Chung-Lung K. Shum,Timothy J. Slegel +7 more
TL;DR: In this paper, a transaction-hint instruction specifies a transaction count-to-completion (CTC) value for a transaction, which indicates how far a transaction is from completion.
References
More filters
Proceedings ArticleDOI
Speculative lock elision: enabling highly concurrent multithreaded execution
Ravi Rajwar,James R. Goodman +1 more
TL;DR: Speculative Lock Elision (SLE) is proposed, a novel micro-architectural technique to remove dynamically unnecessary lock-induced serialization and enable highly concurrent multithreaded execution and can provide programmers a fast path to writing correct high-performance multithreadinged programs.
Proceedings ArticleDOI
Hybrid transactional memory
TL;DR: Using a simulated multiprocessor with HTM support, the viability of the HyTM approach is demonstrated: it can provide performance and scalability approaching that of an unbounded HTM implementation, without the need to support all transactions with complicatedHTM support.
Proceedings ArticleDOI
Transactional Memory Architecture and Implementation for IBM System Z
TL;DR: The implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure, is described.
Patent
Commitment ordering for guaranteeing serializability across distributed transactions
TL;DR: In this paper, serializability across distributed transactions is guaranteed by selectively committing and aborting or delaying transactions to enforce an order of commitment that is the same as the order of performance of conflicting component operations of the transactions.
ReportDOI
Fail-Safe PVM: A Portable Package for Distributed Programming with Transparent Recovery
TL;DR: This work describes the design and implementation of fail-safe PVM (Parallel Virtual Machine), presents measurements of checkpoint costs, and briefly discusses shortcomings and potential avenues for improvement.