Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems

TLDR: Asynchronous processes and their interpretation, as well as the generalization of the Muller theorem, and the modelling of Petri nets, are presented.

Abstract: 1 Introduction- 2 Asynchronous processes and their interpretation- 21 Asynchronous processes- 211 Definition- 212 Some subclasses- 213 Reposition- 214 Structured situations- 215 An asynchronous process as a metamodel- 22 Petri nets- 221 Model description- 222 Some classes- 223 Interpretation- 23 Signal graphs- 24 The Muller model- 25 Parallel asynchronous flow charts- 26 Asynchronous state machines- 27 Reference notations- 3 Self-synchronizing codes- 31 Preliminary definitions- 32 Direct-transition codes- 33 Two-phase codes- 34 Double-rail code- 35 Code with identifier- 36 Optimally balanced code- 37 On the code redundancy- 38 Differential encoding- 39 Reference notations- 4 Aperiodic circuits- 41 Two-phase implementation of finite state machine- 411 Matched implementation- 42 Completion indicators and checkers- 43 Synthesis of combinatorial circuits- 431 Indicatability- 432 Standard implementations- 4321 Minimum form implementation- 4322 Orthogonal form implementation- 4323 Hysteresis flip-flop-based implementation- 4324 Implementation based on "collective responsibility"- 44 Aperiodic flip-flops- 441 Further discussion of flip-flop designs- 4411 RS-flip-flops- 4412 D-flip-flops- 4413 T-flip-flops- 45 Canonical aperiodic implementations of finite state machines- 451 Implementation with delay flip-flops- 452 Implementation using flip-flops with separated inputs- 453 Implementation with complementing flip-flops- 46 Implementation with multiple phase signals- 47 Implementation with direct transitions- 48 On the definition of an aperiodic state machine- 49 Reference notations- 5 Circuit modelling of control flow- 51 The modelling of Petri nets- 511 Event-based modelling- 512 Condition-based modelling- 52 The modelling of parallel asynchronous flow charts- 521 Implementation of standard fragments- 522 A multiple use circuit- 523 A loop control circuit- 524 Using an arbiter- 525 Guard-based implementation- 53 Functional completeness and synthesis of semi-modular circuits- 531 Formulation of the problem- 532 Some properties of semi-modular circuits- 533 Perfect implementation- 534 Simple circuits- 535 The implementation of distributive and totally sequential circuits- 54 Synthesis of semi-modular circuits in limited bases- 55 Modelling pipeline processes- 551 Properties of modelling pipeline circuits- 5511 Pipelinization of parallel fragments- 5512 Pipelinization of a conditional branch- 5513 Transformation of a loop- 5514 Pipelinization for multiply-used sections- 56 Reference notations- 6 Composition of asynchronous processes and circuits- 61 Composition of asynchronous processes- 611 Reinstated process- 612 Process reduction- 613 Process composition- 62 Composition of aperiodic circuits- 621 The Muller theorem- 622 The generalization of the Muller theorem- 63 Algebra of asynchronous circuits- 631 Operations on circuits- 632 Laws and properties- 633 Circuit transformations- 634 Homological algebras of circuits- 64 Reference notations- 7 The matching of asynchronous processes and interface organization- 71 Matched asynchronous processes- 72 Protocol- 73 The matching asynchronous process- 74 The T2 interface- 741 General notations- 742 Communication protocol- 743 Implementation- 75 Asynchronous interface organization- 751 Using the code with identifier- 752 Using the optimally-balanced code- 7521 Half-byte data transfer- 7522 Byte data transfer- 7523 Using non-balanced representation- 76 Reference notations- 8 Analysis of asynchronous circuits and processes- 81 The reachability analysis- 82 The classification analysis- 83 The set of operational states- 84 The effect of non-zero wire delays- 85 Circuit Petri nets- 86 On the complexity of analysis algorithms- 87 Reference notations- 9 Anomalous behaviour of logical circuits and the arbitration problem- 91 Arbiters- 92 Oscillatory anomaly- 93 Meta-stability anomaly- 94 Designing correctly-operating arbiters- 95 "Bounded" arbiters and safe inertial delays- 96 Reference notations- 10 Fault diagnosis and self-repair in aperiodic circuits- 101 Totally self-checking combinational circuits- 102 Totally self-checking sequential machines- 103 Fault detection in autonomous circuits- 104 Self-repair organization for aperiodic circuits- 105 Reference notations- 11 Typical examples of aperiodic design modules- 111 The JK-flip-flop- 112 Registers- 113 Pipeline registers- 1131 Non-dense registers- 1132 Semi-dense pipeline register- 1133 Dense pipeline registers- 1134 One-byte dense pipeline register- 1135 Pipeline register with parallel read-write and the stack- 1136 Reversive pipeline registers- 114 Converting single-rail signals into double-rail ones- 1141 Parallel register with single-rail inputs- 1142 Input and output heads of pipeline registers- 115 Counters- 116 Reference notations- Editor's Epilogue- References