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Institution

Ramtron International

About: Ramtron International is a based out in . It is known for research contribution in the topics: Ferroelectric capacitor & Ferroelectricity. The organization has 156 authors who have published 204 publications receiving 4436 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, the structure and operation of ferroelectric thin-film memory capacitors for use in nonvolatile random-access memory applications are described, as well as possible military and non-military applications of these memories are noted.
Abstract: The structure and operation of ferroelectric thin-film memory capacitors for use in nonvolatile random-access memory applications are described. The search for the ideal ferroelectric material for ferro-electronic memory applications is examined. Possible military and nonmilitary applications of these memories are noted. >

151 citations

Patent
01 Oct 1998
TL;DR: In this paper, a hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in nonvolatile integrated circuit memory devices is presented, which is applicable to all known perovskite dielectrics including PZT, PLZT and layered Perovskites (whether doped or undoped).
Abstract: A hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in non-volatile integrated circuit memory devices. The resultant device structure ameliorates the hydrogen induced degradation of ferroelectric capacitors by completely encapsulating the capacitor within a suitable hydrogen barrier material, such as chemical vapor deposition (“CVD”) or sputtered silicon nitride, thus ensuring process compatibility with industry standard process steps. Although the deposition process for CVD Si3N4 itself contains hydrogen, the deposition time may be kept relatively short thereby allowing the TiN local interconnect layer to act as a “short term” hydrogen barrier. The techniques of the present invention are applicable to all known ferroelectric dielectrics including Perovskites and layered Perovskites (whether doped or undoped) including PZT, PLZT, BST, SBT and others while simultaneously allowing for a potentially broader choice of electrode materials and the use of a forming gas anneal process step on the completed IC structure.

128 citations

Journal ArticleDOI
TL;DR: In this paper, the d31 coefficient of a number of sputtered lead zirconate titanate (PZT) thin films with thicknesses between 0.6 and 3 μm was analyzed.
Abstract: The wafer flexure technique was used to characterize the d31 coefficient of a number of sol–gel and radio frequency (rf) sputtered lead zirconate titanate (PZT) thin films with thicknesses between 0.6 and 3 μm. Typical d31 values for well-poled 52/48 sol–gel films were found to be between −50 and −60 pC/N. The rf sputtered films possessed large as-deposited polarizations which produced d31 coefficients on the order of −70 pC/N in some unpoled films. The subsequent poling of the material, in a direction parallel to the preferred direction increased the d31 coefficient to values of about −85 pC/N. The aging behavior of the d31 coefficient was also investigated. For sol–gel films the aging rate was found to be independent of poling direction and to range from 4% per decade for a 2.5 μm film to 8% per decade for a 0.6 μm film. In contrast, the aging rate of sputtered films was strongly dependent on poling direction, with maximum and minimum rates of 26% and 2% per decade recorded. These aging rates are very h...

123 citations

Journal ArticleDOI
TL;DR: In this article, a low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process.
Abstract: A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

96 citations

Patent
23 Feb 1993
TL;DR: In this article, a method for forming a ferroelectric capacitor for use an integrated circuit establishing one layer over another and then annealing the structure, using an oxygen or ozone anneal, after each layer is established.
Abstract: A method for forming a ferroelectric capacitor for use an integrated circuit establishing one layer over another and then annealing the structure, using an oxygen or ozone anneal, after each layer is established. In particular, an ozone anneal is used after the establishment of a layer of ferroelectric material.

95 citations


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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
201218
20105
20091
20083
20074
20051