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Semiconductor floating gate storage device with lateral electrode system

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TLDR
In this article, the recording and erasing voltage is applied between two juxtaposed surface zones of the same conductivity type present outside the channel region and the source and drain zones, one of the surface zones, which is preferably also the source or drain zone, being separated from the floating gate electrode by an insulating layer having a thickness of less than 0.01 micron through which charge carriers can tunnel.
Abstract
A semiconductor storage device having a field-effect transistor with a floating insulating gate electrode on which information-containing charge can be stored by tunneling charge carriers between the semiconductor body and the gate electrode. According to the invention the recording and erasing voltage is applied between two juxtaposed surface zones of the same conductivity type present outside the channel region and the source and drain zones, one of the surface zones, which is preferably also the source or drain zone, being separated from the floating gate electrode by an insulating layer having a thickness of less than 0.01 micron through which charge carriers can tunnel. Recording and erasing can be carried out at low voltages and with a voltage source of the same polarity relative to a reference potential.

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Citations
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Chiu Te-Long
TL;DR: In this article, a method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electricallyprogrammable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71).
References
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Patent

Stabilized semiconductor devices and method of making same

TL;DR: In this article, a selective doping of the transverse side surfaces of the channel region of a field effect transistor (FET) was proposed to reduce leakage current and threshold voltage of the FET.
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Method for forming MOS structure using double diffusion

TL;DR: In this article, a gate oxide layer is formed on the gate oxide to protect it from being etched and also from contamination, and an opening is provided which exposes the surface of the semiconductor body adjacent to gate oxide.
Patent

Avalanche injection type mos memory

Fujio Masuoka
TL;DR: Avalanche injection type MOS memory having a floating gate surrounded by an insulating layer between the source and drain regions formed on one side of a semiconductor substrate wherein there is formed one or two auxiliary semiconductor regions with the same type of conductivity as, but with higher concentrations of impurities than, said semiconductor substrates.
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Electrically alterable floating gate device and method for altering same

TL;DR: In this paper, a field effect device having a floating gate which can be charged or discharged electrically is disclosed. But the floating gate can be discharged by the application of a voltage to the second gate relative to the spaced apart regions and substrate.
Patent

Field effect semiconductor memory apparatus with a floating gate

F Masuoka
TL;DR: In this paper, a field effect semiconductor memory with a floating gate and a gate electrode is constructed such that when the gate electrodes are impressed with voltage, there is an electric field stronger than, or at least as strong as, that prevailing across the gate and gate electrode.