Patent
Semiconductor memory device
TLDR
In this article, a semiconductor memory device comprising a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to the bit line, a read transistor with gate connecting to a second impurity area forming a drain of the write transistor and a capacitor connected between the gate and the read transistor is described.Abstract:
A semiconductor memory device comprising a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to a bit line, a read transistor with a gate connected to a second impurity region forming a source or drain of the write transistor, a first impurity region connected to a read word line, and a second impurity region connected to a bit line, and a capacitor connected between the gate and the second impurity region of the read transistor.read more
Citations
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References
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Patent
Three transistor multi-state dynamic memory cell for embedded CMOS logic applications
TL;DR: In this paper, a three transistor cell was used for multi-state dynamic memory with different levels of write levels, read levels, reference devices, and sense amplifier design, and two cell enhancements were proposed: substituting a PFET in place of and NFET for the write select transistor, and adding a capacitor for extended refresh times.
Patent
Semiconductor memory device
TL;DR: In this article, the problem of providing a circuit structure by which a state after a fuse is cut off and a state before a fuse can be realized arbitrarily regardless of the existence of the cut-off of a fuse was addressed.
Patent
Semiconductor memory device having an internal amplification function
TL;DR: In this article, a double gate thin film transistor, having the same channel conductivity type as that of the insulated gate field effect transistor, is formed above the double gate gate.
Patent
Highly integrated cell having a reading transistor and a writing transistor
TL;DR: In this paper, a DRAM cell consisting of an input/output bit line, a first word line, and a second word line was activated by a read control signal was presented.
Patent
Dynamic random access memory having a gain function
TL;DR: In this article, a three transistor type memory cell is used instead of a conventional lT-lC memory cell, and data read and write terminals are connected to a pair of data lines in such a manner that the electrical characteristics of the pair of lines are balanced.