Patent
Semiconductor wafer bonding incorporating electrical and optical interconnects
TLDR
In this paper, the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optic signals between the bonded wafers is discussed. But the authors do not consider the transfer of optical signals across the bonding interface.Abstract:
Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods for bonding of semiconductor wafers incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed across the bonding surface using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed across the bonding surface using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.read more
Citations
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Patent
Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby
Sampath Purushothaman,Roy Yu +1 more
TL;DR: In this article, a process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer of a top silicon Wafer comprising a silicon-on-insulator (SOI) wafer.
Patent
Light-emitting diode display panel with micro lens array
Lei Zhang,Fang Ou,Qiming Li +2 more
TL;DR: In this paper, a light-emitting diode (LED) display panel includes a substrate, a driver circuit array array on the substrate and including a plurality of pixel driver circuits arranged in an array, an LED array including an array of LED dies each being coupled to one of the pixel drivers, and an optical spacer formed between the LED array and the micro lens array.
Patent
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John E. Bowers,Jock Bovington +1 more
TL;DR: In this paper, a method of fabricating a heterogeneous semiconductor wafer includes depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate.
Patent
Non-Telecentric Emissive Micro-Pixel Array Light Modulators and Methods of Fabrication Thereof
TL;DR: In this article, an emissive multi-color micro-pixel spatial light modulator with non-telecentric emission is introduced. But the individual light emission from each multi-colour micro-scale modulator is directionally modulated in a unique direction.
Patent
Semiconductor apparatus and method of manufacturing the same
TL;DR: A semiconductor apparatus includes a driver circuit wafer including a plurality of driver circuits arranged in an array, a bonding metal layer formed over the driver circuit, and a horizontally continuous functional device epi-structure layer forming over the metal layer and covering the driver circuits.
References
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Book
SemiConductor Wafer Bonding: Science and Technology
Q.-Y Tong,Ulrich Gösele +1 more
TL;DR: In this paper, the authors present the basic interactions between flat surfaces, including the influence of Particles, Surface Steps, and Cavities, and thermal treatment of Bonded Wafer Pairs.
Patent
Bonded intermediate substrate and method of making same
Thomas Henry Pinnington,James M. Zahler,Young-Bae Park,Charles S. Tsai,Corinne Ladous,Harry Jr. A. Atwater,Sean Olson +6 more
TL;DR: In this article, an intermediate substrate is defined as a handle substrate bonded to a thin layer suitable for epitaxial growth of a compound semiconductor layer, such as a III-nitride semiconductor.
Patent
Method for low temperature bonding and bonded structure
TL;DR: In this paper, a method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching, which may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2.
Patent
Low temperature silicon wafer bond process with bulk material bond strength
TL;DR: In this paper, a method for bonding one semiconductor surface to another is presented, where the semiconductor surfaces are annealed with an energy source wherein energy is confined to the surfaces.
Patent
3D IC method and device
TL;DR: In this paper, a method of three-dimensional integration of elements such as singulated die or wafers and an integrated structure having connected elements, including singulated dies or wafer, was proposed.