A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

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Sub-Atmospheric Chemical Vapor Deposition Process for Chip-to-Wafer 3-Dimensional Integration

Three-dimensional integration technology and integrated systems

We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5?m. We have fabricated 3-D LSI test chips by a super-chip integration technology.

Three-Dimensional Integration Technology Using Self-Assembly Technique and Super-Chip Integration

We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100 %. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology).

Sub-Atmospheric Chemical Vapor Deposition Process for Chip-to-Wafer 3-Dimensional Integration

Citations

Three-dimensional integration technology and integrated systems

Three-Dimensional Integration Technology Using Self-Assembly Technique and Super-Chip Integration

New three-dimensional integration technology using reconfigured wafers

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