Three-dimensional integration technology and integrated systems
Mitsumasa Koyanagi,Takafumi Fukushima,Tetsu Tanaka +2 more
- pp 409-415
TLDR
A three-dimensional integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs and a new reconfigurable parallel image processing system is proposed.Abstract:
A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.read more
Citations
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Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Journal ArticleDOI
3-D Integration and Through-Silicon Vias in MEMS and Microsensors
TL;DR: The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics as discussed by the authors.
References
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Journal ArticleDOI
Future system-on-silicon LSI chips
TL;DR: In this work, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using a new three-dimensional integration technology to overcome future wiring connectivity crises.
Journal ArticleDOI
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
Mitsumasa Koyanagi,T. Nakamura,Yusuke Yamada,H. Kikuchi,Takafumi Fukushima,Tetsu Tanaka,Hiroyuki Kurino +6 more
TL;DR: In this article, a 3D shared-memory test chip with three-stacked layers was fabricated by bonding the wafers with vertical buried interconnections after thinning.
Proceedings ArticleDOI
Three-dimensional shared memory fabricated using wafer stacking technology
K. W. Lee,T. Nakamura,Teruo Ono,Yusuke Yamada,T. Mizukusa,H. Hashimoto,Ki-Tae Park,Hiroyuki Kurino,Mitsumasa Koyanagi +8 more
TL;DR: It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.
Proceedings ArticleDOI
Neuromorphic vision chip fabricated using three-dimensional integration technology
Mitsumasa Koyanagi,Yoshihiro Nakagawa,K. W. Lee,T. Nakamura,Y. Yamada,K. Inamura,Ki-Tae Park,Hiroyuki Kurino +7 more
TL;DR: In this paper, a 3D integration technology for image processing and pattern recognition with parts of functions of the retina and visual cortex using silicon is presented. And the three-dimensional (3D) integration technology achieved an image processing, pattern recognition, and pattern classification system using parts of functional units of the human brain using silicon.
Proceedings ArticleDOI
Intelligent image sensor chip with three dimensional structure
Hiroyuki Kurino,Kang-Wook Lee,T. Nakamura,Katsuyuki Sakuma,Ki-Tae Park,Nobuaki Miyakawa,Shimazutsu Hiroaki,K.Y. Kim,K. Inamura,Mitsumasa Koyanagi +9 more
TL;DR: A 3D image sensor test chip was fabricated using this 3D integration technology in this paper, and basic electric characteristics were evaluated in the test chip using the three-dimensional integration technology.
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