Patent
Thermal oxide equivalent low temperature ALD oxide for dual purpose gate oxide and method for producing the same
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TLDR
In this article, conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. But they do not specify the fabrication process.Abstract:
Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOx layer over the second silicon oxy-nitride layer and ILs.read more
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Methods for thermally calibrating reaction chambers
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Method of processing a substrate and a device manufactured by using the method
Seung Ju Chun,Yong Min Yoo,Jongwan Choi,Young Jae Kim,Sun Ja Kim,Wan Gyu Lim,Yoon Ki Min,Hae Jin Lee,Tae Hee Yoo +8 more
TL;DR: In this paper, a method of processing a substrate by omitting a photolithographic process is disclosed, which includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface.
References
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Patent
Semiconductor device, and manufacturing method thereof
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Patent
Methods for forming a semiconductor device and related semiconductor device structures
TL;DR: In this paper, methods for forming semiconductor devices and related semiconductor device structures are provided. In some embodiments, methods may include, removing the first work function metal over the NMOS gate dielectric and forming a second work-function metal over a substrate.
Patent
Semiconductor device with tunable work function
TL;DR: The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, barrier layer and a silicide layer as discussed by the authors.
Patent
Vertical transistor device
TL;DR: In this paper, a method for forming a semiconductor device includes pattering a first fin in the semiconductor substrate and forming a liner layer over the first fin, which is then removed to form a first cavity.
Patent
Vertical fin field effect transistor with air gap spacers
TL;DR: A fin field effect transistor (FFE transistor) as mentioned in this paper is a transistor with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the vertical fin, and a bottom void space between the source layer and the gate metal filling.