Towards a notion of unsatisfiable and unrealizable cores for LTL
TLDR
Investigation of notions of unsatisfiable cores for LTL that arise from the syntax tree of an LTL formula, from converting it into a conjunctive normal form, and from proofs of its unsatisfiability, which are more fine-grained than existing ones.About:
This article is published in Science of Computer Programming.The article was published on 2012-07-01 and is currently open access. It has received 40 citations till now. The article focuses on the topics: Conjunctive normal form & Realizability.read more
Citations
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Book ChapterDOI
Evaluating LTL satisfiability solvers
Viktor Schuppan,Luthfi Darmawan +1 more
TL;DR: It turns out that even combining two solvers in a simple fashion significantly increases the share of solved instances while reducing CPU time spent, and no solver dominates or solves all instances.
Book ChapterDOI
Trace Diagnostics Using Temporal Implicants
TL;DR: An inductive procedure for finding temporal implicants is obtained by the introduction of selection functions that appear in a process equivalent to Skolemization in first order logic, and is able to generate concise implicant of a property, describing a small fragment of the input signal that causes violation of a formula.
Proceedings Article
Behavioral diagnosis of LTL specifications at operator level
Ingo Pill,Thomas Quaritsch +1 more
TL;DR: This paper proposes a scenario-based diagnosis at a specification's operator level using weak or strong fault models using efficient SAT encodings, and shows how to achieve that effectively for specifications in LTL.
Journal ArticleDOI
Analysing sanity of requirements for avionics systems
TL;DR: This work proposes new sanity checking techniques that automatically detect flaws and suggest improvements of given requirements and describes a semi-automatic completeness evaluation that can assess the coverage of user requirements and suggest missing properties the user might have wanted to formulate.
Proceedings ArticleDOI
Proving and explaining the unfeasibility of message sequence charts for hybrid systems
TL;DR: In this article, the authors propose an approach to prove that a message sequence chart (MSC) can not be satisfied by any trace of a given hybrid automata network, and explain why an MSC is unfeasible.
References
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Model checking
TL;DR: Model checking tools, created by both academic and industrial teams, have resulted in an entirely novel approach to verification and test case generation that often enables engineers in the electronics industry to design complex systems with considerable assurance regarding the correctness of their initial designs.
Proceedings ArticleDOI
The temporal logic of programs
TL;DR: A unified approach to program verification is suggested, which applies to both sequential and parallel programs, and the main proof method is that of temporal reasoning in which the time dependence of events is the basic concept.
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Principles of Model Checking
TL;DR: Principles of Model Checking offers a comprehensive introduction to model checking that is not only a text suitable for classroom use but also a valuable reference for researchers and practitioners in the field.
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Temporal and modal logic
TL;DR: In this article, a multiaxis classification of temporal and modal logic is presented, and the formal syntax and semantics for two representative systems of propositional branching-time temporal logics are described.
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Symbolic model checking: 10/sup 20/ states and beyond
TL;DR: In this paper, a model-checking algorithm for mu-calculus formulas which uses R.E. Bryant's (1986) binary decision diagrams to represent relations and formulas symbolically is described.